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研究業績 (リンクをクリックすると学会のページに移動します。)


【2022年】

学術論文誌

  • N. Onizawa, K. Katsuki, D. Shin, W. Gross, and T. Hanyu, "Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing," IEEE Transactions on Neural Networks and Learning Systems, 2022. (in press) doi: 10.1109/TNNLS.2022.3159713
  • D. Suzuki, T. Oka, and T. Hanyu, "Design of an Active-Load-Localized Single-Ended Nonvolatile Lookup-Table Circuit for Energy-Efficient Binary-Convolutional-Neural-Network Accelerator" Japanese Journal of Applied Physics (JJAP), vol.61, no.SC, pp.1083-1~1083-10 (10pages), 2022. doi: 10.35848/1347-4065/ac51bf
  • F. Zhong, M. Natsui, and T. Hanyu, "Dynamic Activation of Power-Gating-Switch Configuration for Highly Reliable Nonvolatile Large-Scale Integrated Circuits," Japanese Journal of Applied Physics (JJAP), vol.61, no.SC, pp.1035-1~1035-10 (10 pages), 2022. doi: 10.35848/1347-4065/ac461a
  • N. Onizawa and T. Hanyu, "CMOS Invertible Logic: Bidirectional Operation Based on Probabilistic Device Model and Stochastic Computing," IEEE Nanotechnology Magazine, vol. 16, issue 1, pp. 33-46, Feb. 2022. doi: 10.1109/MNANO.2021.3126094

国際会議(査読あり)

招待講演/招待講義

  • T. Hanyu, "Prospects of MTJ-Based Nonvolatile Logic-in-Memory Circuits and Their Applications to AI Hardware," The 3rd International Sympodium on AI and Electronics, Feb. 15, 2022.


【2021年】

学術論文誌

  • N. Onizawa, A. Tamakoshi, and T. Hanyu, "Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices," IEEE Open Journal of Circuits and Systems, Vol.2, pp.782-791, Dec. 2021. DOI: 10.1109/OJCAS.2021.3116584
  • D. Suzuki, T. Oka, A. Tamakoshi, Y. Takako, and T. Hanyu, "Design framework for an energy-efficient binary convolutional neural network accelerator based on nonvolatile logic," Nonlinear Theory and Its Applications (NOLTA), IEICE, vol.E12-N, no.4, pp.695--710, Oct. 2021. DOI: 10.1587/nolta.12.695
  • D. Suzuki and T. Hanyu, "Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow," IEICE Trans. Inf. & Syst., vol. E104-D, no. 8, pp. 1111-1120, Aug. 2021. DOI: 10.1587/transinf.2020LOP0010
  • M. Kato, N. Onizawa, and T. Hanyu, "Design automation of invertible logic circuit from a standard HDL description," Journal of Applied Logics, vol.8, no.5, pp.1311-1333 (23 pages), June 2021.
  • 夏井雅典, 羽生貴弘, "不揮発記憶機能が拓く新概念ロジックLSI設計技術とその将来展望," 電子情報通信学会論文誌 C, vol.J104-C, no.06, June 2021. DOI: 10.14923/transelej.2020JCI0011
  • M. Natsui, A. Tamakoshi, H. Honjo, T. Watanabe, T. Nasuno, C. Zhang, T. Tanigawa, H. Inoue, M. Niwa, T. Yoshiduka, Y. Noguchi, M. Yasuhira, Y. Ma, H. Shen, S. Fukami, H. Sato, S. Ikeda, H. Ohno, T. Endoh, T. Hanyu, "Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under Field-Assistance -Free Condition" IEEE Journal of Solid-State Circuits, vol. 56, no. 4, pp.1116-1128, April 2021. DOI: 10.1109/JSSC.2020.3039800
  • N. Onizawa, K. Nishino, S. C. Smithson, B. H. Meyer, W. J. Gross, H. Yamagata, H. Fujita, and T. Hanyu, "A Design Framework for Invertible Logic," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.40, issue 4, pp.655-665, April 2021. DOI 10.1109/TCAD.2020.3003906
  • D. Suzuki, T. Oka, and T. Hanyu, "Design of an Energy-Efficient Binarized Convolutional Neural Network Accelerator Using a Nonvolatile Field-Programmable Gate Array with Only-Once-Write Shifting" Japanese Journal of Applied Physics (JJAP), vol.60, pp.SBBB07-1~SBBB07-9 (9pages), March 2021. DOI: 10.35848/1347-4065/abe682
  • M. Natsui, G. Yamagishi,and Takahiro Hanyu, "Design of a Highly Reliable Nonvolatile Flip-Flop Incorporating a Common-Mode Write Error Detection Capability," Japanese Journal of Applied Physics, vol.60, pp.SBBB02-1~SBBB02-9 (9pages), Feb. 2021. DOI: 10.35848/1347-4065/abdcb0
  • R. Arakawa, N. Onizawa, J.-P. Diguet, and T. Hanyu, "Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN," IEEE Trans. Circuits and Systems I, vol.68, issue 1, pp.67-76, Jan. 2021. DOI: 10.1109/TCSI.2020.3030104

国際会議(査読あり)

  • D. Suzuki, T. Oka, and T. Hanyu, "A Memory-Access-Minimized BCNN Accelerator Using Nonvolatile FPGA with Only-Once-Write Shifting," Proc. of IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC2021), pp.92-97, Dec. 20-23, 2021.
  • D. Suzuki, T. Oka, and T. Hanyu, "Design of an Energy-Efficient Nonvolatile-FPGA-Based BCNN Accelerator Using an Active-Load-Localized Single-Ended Circuit Style," Extended Abstract of 2021 International Conference on Solid State Devices and Materials (SSDM 2021), pp.670-671, Sept. 2021.
  • F. Zhong, M. Natsui, and T. Hanyu, "Dynamic Power-Gating-Switch Control Technique and Its Application to an Energy-Efficient Embedded STT-MRAM," Extended Abstracts of the 2021 International Conference on Solid State Devices and Materials (SSDM 2021), pp. 672-673, Sept. 2021.
  • N. Onizawa and T. Hanyu, "High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians," 2021 International Conference on Circuits and Systems (ISCAS2021), 5pages, May 25, 2021.

招待講演/招待講義

  • T. Hanyu, "Challenge of MTJ-Based Nonvolatile Logic-in-Memory Circuits and Their Applications," Joint Seminar of BRAIN INSPIRED COMPUTING, PHYSICS, ARCHITECTURES, MATERIALS AND APPLICATIONS (BICPAMA), Dec. 8, 2021.
  • (Keynote Speech) T. Hanyu, "Challenge of MTJ-Based Nonvolatile Logic-in-Memory Circuits and Their Applications," IEEE International Symposium on Nanotechnology Architecture, Nov. 10, 2021.
  • 鬼沢直哉, "CMOSインバーティブルロジックとその学習ハードウェアへの応用展開," 第42回IBISML研究会, 1page, 2021年3月.


【2020年】

学術論文誌

  • K. A. Ali, M. Rizk, A. Baghdadi, J.-P. Diguet, J. Jomaah, N. Onizawa, and T. Hanyu,"Memristive Computational Memory Using Memristor Overwrite Logic (MOL)", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 28, Issue 11, pp. 2370-2382, Nov. 2020.
  • D. Shin, N. Onizawa, W. J. Gross, and T. Hanyu,"Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic," IEEE Access, vol.8, pp.188004-188014, Oct. 2020. DOI: 10.1109/ACCESS.2020.3029576
  • N. Onizawa, S. Mukaida, A. Tamakoshi, H. Yamagata, H. Fujita, and T. Hanyu, "High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 28, Issue 10, pp. 2171-2181, Oct. 2020. DOI: 10.1109/TVLSI.2020.3005413
  • N. Onizawa, S. Smithson, W. Gross, B. Meyer, and T. Hanyu, "In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning," IEEE Trans. Circuits and Systems I, vol. 67, no. 5, pp.1541-1550, May 2020. DOI:10.1109/TCSI.2019.2960383
  • 羽生貴弘, "不揮発性ロジックでひらくエッジAI ハード ウェアの展望," 電子情報通信学会, Fundamentals Review, Vol.13, No.4, pp.269-276, April 2020.(解説論文)
  • M. Natsui, T. Chiba, and T. Hanyu,"Impact of MTJ-Based Nonvolatile Circuit Techniques for Energy-Efficient Binary Neural Network Hardware," Japanese Journal of Applied Physics (JJAP), STAP article, vol.59, pp.050602-1~7, April 2020.
  • D. Suzuki and T. Hanyu, "Design of a Cost-Efficient Controller for Realizing a Data-Shift-Minimized Nonvolatile Field-Programmable Gate Array," Japanese Journal of Applied Physics (JJAP), vol. 59, no. SG, pp. SGGB13-1~SGGB13-7, April 2020. DOI: 10.35848/1347-4065/ab70ac

国際会議(査読あり)

  • T. Oka, D. Suzuki, and T. Hanyu, "Challenge of Energy-Efficient Edge-AI Hardware Using Spintronics-Based Nonvolatile Logic," 2020 International Symposium on Nonlinear Theory and Its Applications (NOLTA 2020), pp.85-88, Nov. 2020.
  • G. Yamagishi, M. Natsui and T. Hanyu, "Design of a Magnetic-Tunnel-Junction-Based Nonvolatile Flip-Flop with Common-Mode Write Error Detection," Extended Abstract of 2020 International Conference on Solid State Devices and Materials (SSDM 2020), pp.87-88, Sept. 2020.
  • D. Suzuki, T. Oka, and T. Hanyu, "Design of an Energy-Efficient Binarized Convolutional Neural Network Acceler-ator Using a Nonvolatile FPGA with Only-Once-Write Shifting," Extended Abstract of 2020 International Conference on Solid State Devices and Materials (SSDM 2020), pp.91-92, Sept. 2020.
  • Y. Takako, D. Suzuki, M. Natsui and T. Hanyu, "Systematic Design Flow for Realizing MTJ-Based Nonvolatile FPGAs," Extended Abstract of 2020 International Conference on Solid State Devices and Materials (SSDM 2020), pp.93-94, Sept. 2020.
  • A. Tamakoshi, N. Onizawa, H. Yamagata, H. Fujita, and T. Hanyu, "Design of an Energy-Efficient True Random Number Generator Based on Triple Read-Write Data-Stream Multiplexing of MTJ Devices," Proc. 18th IEEE International New Circuits and Systems Conference (NEWCAS), pp.283-286, June 2020.
  • M. Natsui, A. Tamakoshi, H. Honjo, T. Watanabe, T. Nasuno, C. Zhang, T. Tanigawa, H. Inoue, M. Niwa, T. Yoshiduka,Y. Noguchi, M. Yasuhira, Y. Ma, H. Shen,S. Fukami, H. Sato, S. Ikeda, H. Ohno, T. Endoh, and T. Hanyu, "Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage," 2020 Symposium on VLSI Circuits, Digest of Technical Papers, 2 pages, June 2020.
  • D. Suzuki and T. Hanyu, "Design and Evaluation of a Synthesizable Standard-Cell-Based Nonvolatile FPGA," Proceedings of the 50th International Symposium on Multiple-Valued Logic (ISMVL), pp. 194-199, May 2020.

招待講演/招待講義

  • T. Hanyu, "Impact of a nonvolatile multiple-valued circuit technique for energy-efficient binarized neural-network hardware," ENGE 2020(The 6th International Conference on Electronnic Materials and Nanotechnology for Green Environment), Nov.1-4, 2020.
  • T. Hanyu, "Challenge of Nonvolatile Logic LSI for Edge AI Applications," U. of A. Research Cluster Forum (web会議形式), Oct. 24, 2020.
  • 羽生貴弘, "不揮発性ロジックが拓く脳型コンピューティングの挑戦," 第7回電子デバイスフォーラム京都 (web会議形式), Oct. 30, 2020.


【2019年】

学術論文誌

国際会議(査読あり)

  • H. Honjo, T. Nguyen, T. Watanabe, T. Nasuno, C. Zhang, T. Tanigawa, S. Miura, H. Inoue, M. Niwa, T. Yoshiduka, Y. Noguchi, M. Yasuhira, A. Tamakoshi, M. Natsui, Y. Ma, H. Koike, Y. Takahashi, K. Furuya, H. Shen, S. Fukami, H. Sato, S. Ikeda , T. Hanyu, H. Ohno, and T. Endoh, "First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology," iedm 2019, Dec. 2019.
  • N. Onizawa, W. Gross, and T. Hanyu, "Stochastic-Computing Based Brainwave LSI Towards an Intelligence Edge," Proceeding of the 26th IEEE International Conference on Electronics Circuits and Systems (ICECS), 4 pages, Nov. 2019.
  • D. Shin, N. Onizawa, and T. Hanyu, "FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic," 26th IEEE International Conference on Electronics Circuits and Systems (ICECS), 2 pages, Nov. 2019.
  • R. Arakawa, N. Onizawa, J. Diguet, and T. Hanyu, "Multi-Context TCAM Based Selective Computing Architecture for a Low-Power NN," 26th IEEE International Conference on Electronics Circuits and Systems (ICECS), 2 pages, Nov. 2019.
  • N. Onizawa, K. Nishino, S. Smithson, B. Meyer, W. Gross, H. Yamagata, H. Fujita, and T. Hanyu, "A Design Framework for Invertible Logic," Proc. of the 53rd Asilomar Conference on Signals, Systems and Computers, 4 pages, Nov. 2019.
  • M. Natsui and T. Hanyu, "MTJ-Based Nonvolatile Logic-in-Memory Circuit with Feedback-Type Equal-Resistance Sensing Mechanism for Ternary Neural Network Hardware," IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2 pages, Oct. 2019.
  • D. Suzuki and T. Hanyu, "Design of an Energy-Efficient Controller for Realizing a Data-Shift-Minimized Nonvolatile FPGA," Extended Abstracts of 2019 International Conference on Solid State Devices and Materials (SSDM2019), pp. 525-526, Sep. 2019.
  • T. Chiba, M. Natsui, and T. Hanyu, "Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks," Proceedings of the 49th International Symposium on Multiple-Valued Logic (ISMVL), pp. 91-96, May 2019.
  • M. Natsui, D. Suzuki, A. Tamakoshi, T. Watanabe, H. Honjo, H. Koike, T. Nasuno, Y. Ma, T. Tanigawa, Y. Noguchi, M. Yasuhira, H. Sato, S. Ikeda, H. Ohno, T. Endoh, and T. Hanyu, "An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJHybrid Technology Achieving 47.14μW Operation at 200MHz," 2019 IEEE International Solid-State Circuits Conference (ISSCC2019), pp. 202-203, Feb. 2019.

招待講演/招待講義

  • M. Natsui, "Nonvolatile Logic LSI Design Technology and Its Application to AI Hardware," 2019 International Conference on Solid State Devices and Materials (SSDM2019), Short Courses, Sep. 2019.
  • N. Onizawa, "Stochastic Computing for Brainware LSI," RIKEN IMS-JSI International Symposium on Immunology 2019, 1 page, Mar. 2019.
  • M. Natsui, "An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJHybrid Technology Achieving 47.14μW Operation at 200MHz," IEEE SSCS Kansai Chapter Technical Seminar, Mar. 2019.


【2018年】

学術論文誌

国際会議(査読あり)

招待講演/招待講義

  • 羽生貴弘, 鬼沢直哉, 鈴木大輔, 夏井雅典, "ポストCMOS回路技術が拓く AIハードウェアの挑戦," デザインガイア2018, Dec. 2018.
  • T. Hanyu, "Challenge of an MTJ-Based Non-Volatile Logic LSI for Internet-of-Things Application," Workshop on Next Generation Computing System, Nov. 2018.
  • T. Hanyu, "Design of an MTJ-Based Nonvolatile Logic LSI and Its Application," 2018 18th Non-Volatile Memory Technology Symposium (NVMTS2018), p. 40, Oct. 2018.
  • T. Hanyu, "Prospects of Nonvolatile Logic LSI Using MTJ/MOS-Hybrid Circuitry and Its Application," Extended Abstracts of 2018 International Conference on Solid State Devices and Materials (SSDM2018), B-4-01, pp. 115-116, Sep. 2018.
  • T. Hanyu, T. Endoh, D. Suzuki, M. Natsui, and H. Ohno, "Impact of an MTJ-based logic LSI and its possibility," Proc. of the 7th IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA), Aug. 2018.
  • M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, "MTJ-Based Nonvolatile Logic LSI for Ultra Low-Power and Highly Dependable Computing," China Semiconductor Technology International Conference (CSTIC), pp. 1-54, Mar. 2018.
  • 夏井雅典, 羽生貴弘, "次世代IoT社会に向けた脳型LSI設計技術," 2018年電子情報通信学会総合大会, Mar. 2018.


【2017年】

学術論文誌

国際会議(査読あり)

  • N. Onizawa, S. Koshita, S. Sakamoto, M. Kawamata, and T. Hanyu, "Design of Stochastic Asymmetirc Compensation Filter for Auditory SignalProcessing," Proc. 5th IEEE Global Conference on Signal and Information Processing (GlobalSIP), pp. 1315-1319, Nov. 2017.
  • M. Natsui and T. Hanyu, "Energy-Efficient High-Performance Nonvolatile VLSI Processor with a Temporary-Data Reuse Technique," Extended Abstracts of 2017 International Conference on Solid State Devices and Materials (SSDM2017), pp. 977-978, Sep. 2017.
  • D. Suzuki and T. Hanyu, "Design of an MTJ-Oriented Nonvolatile Lookup Table Circuit with Write-Operation Minimizing," Extended Abstracts of the 2017 International Conference on Solid State Devices and Materials (SSDM2017), pp. 195-196, Sep. 2017.
  • N. Onizawa, K. Matsumiya, W. J. Gross, and T. Hanyu, "Accuracy/Energy-Flexible Stochastic Configurable 2D Gabor Filter with Instant-on Capability ," Proc. 43rd European Solid-State Circuit Conference (ESSCIRC), pp. 43-46, Sep. 2017.
  • M. Rizk, J.-P. Diguet, N. Onizawa, M. J. Sepulveda, Y. Akgul, V. Gripon, A. Baghdadi, and T. Hanyu, "NoC-MRAM Architecture for Memory-Based Computing: Database-Search Case Study," Proc. 15th IEEE International New Circuits and Systems Conference (NEWCAS), pp. 309-312, June 2017.
  • N. Onizawa, S. Koshita, S. Sakamoto, M. Kawamata, and T. Hanyu, "Evaluation of Stochastic Cascaded IIR Filters," 47th IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 2017.
  • N. Onizawa, M. Imai, T. Hanyu and T. Yoneda, "MTJ-based asynchronous circuits for re-initialization free computingagainst power failures," Proc. of 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 118-125, May 2017.

招待講演/招待講義

  • 夏井雅典, "脳型LSIを拓く集積回路・アーキテクチャの展望," VLSI夏の学校「LSI技術者のための人工知能基礎講座」, Aug. 2017.
  • T. Hanyu, "Challenge of MTJ-Based Nonvolatile Logic LSI for IoT Applications," Tohoku-Hanyang Workshop on Electronics and Communications Engineering (WECE), Aug. 2017.
  • T. Hanyu, "Challenge of Spintronics-Based Nonvolatile VLSI Processor with a Sudden Power-Outage Resilient In-Processor Checkpointing," 2017 Spintronics Workshop on LSI, p. 3, June 2017.
  • T. Hanyu, "Challenge of MOS/MTJ-Hybrid Nonvolatile VLSI Processor for IoE Applications," Emerging Technologies of Communications, Microsystems, Optoelectronics and Sensors 2017 (ETCMOS 2017), May 2017.
  • D. Suzuki and T. Hanyu, "MTJ-Based Nonvolatile FPGA; the Present and the Future Technology Trends," 26th International Workshop on Post-Binary ULSI Systems, p. 2, May 2017.
  • T. Hanyu, "MTJ-Based Nonvolatile Logic-in-Memory Circuits with Self-Terminated Writing Mechanism for Ultra-Low-Power VLSI Processor," Special lecture at Nazarbayev Univ., May 2017.
  • T. Hanyu, "Challenge of Spintronics-Device-Based Non-volatile Logic-in-Memory Architecture for Internet-of-Things Applications," BIT's 3rd Annual World Congress of Smart Materials-2017, p. 262, Mar. 2017.
  • T. Hanyu, D. Suzuki, N. Onizawa, and M. Natsui, "Three-Terminal MTJ-Based Nonvolatile Logic Circuits with Self-Terminated Writing Mechanism for Ultra-Low-Power VLSI Processor," Design, Automation & Test in Europe (DATE), pp. 548-553, Mar. 2017.


【2016年】

学術論文誌

  • K. Boga, F. Leduc-Primeaur, N. Onizawa, K. Matsumiya, T. Hanyu, and W. J. Gross, "A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception," Journal of Signal Processing Systems (JSPS), Dec. 2016.
  • T. Hanyu, T. Endoh, D. Suzuki, H. Koike, Y. Ma, N. Onizawa, M. Natsui, S. Ikeda, and H. Ohno, "Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing," Proc. IEEE, Vol. 104, No. 10, pp. 1844-1863, Oct. 2016.
  • N. Onizawa, D. Katagiri, W. J. Gross, and T. Hanyu, "Analog-to-Stochastic Converter Using Magnetic Tunnel Junction Devices for Vision Chips," IEEE Trans. on Nanotechnology, Vol. 15, No. 5, pp. 705-714, Sep. 2016.
  • T. Endoh, H. Koike, S. Ikeda, T. Hanyu, and H. Ohno, "An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories -," IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), Vol. 6, No. 2, pp. 109-119, June 2016.
  • N. Onizawa, H. Jarollahi, T. Hanyu, and W. J. Gross, "Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks," IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), Vol. 6, No. 1, pp. 13-24, Mar. 2016.
  • Y. Ma, S. Miura, H. Honjo, S. Ikeda, T. Hanyu, H. Ohno, and T. Endoh, "A 600-µW Ultra-Low-Power Associative Processor for Image Pattern Recognition Employing MTJ-Based Nonvolatile Memories with Autonomic Intelligent Power-Gating (IPG) Scheme," Japanese Journal of Applied Physics (JJAP), Vol. 55, No. 4S, 04EF15-1-11, Mar. 2016.
  • N. Onizawa, N. Sakimura, R. Nebashi, T. Sugibayashi, and T. Hanyu, "Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory," Journal of Multiple Valued-Logic & Soft Computing (MVLSC), Vol. 26, Issue 1/2, pp. 125-140, 2016.

国際会議(査読あり)

  • D. Suzuki and T. Hanyu, "A Self-Terminated One-Phase Write Driver for Complementary-MTJ Based Memory Cells," Abst. 61st Annual Conference on Magnetism & Magnetic Materials (MMM), p. 554, Nov. 2016.
  • D. Suzuki and T. Hanyu, "A Self-Terminated Energy-Efficient Nonvolatile Flip-Flop Using 3-terminal Magnetic Tunnel Junction Device," Proc. of 2016 International Conference on Solid State Devices and Materials (SSDM2016), pp. 911-912, Sep. 2016.
  • N. Onizawa and T. Hanyu, "A Soft/Write-Error Resilient CMOS/MTJ Nonvolatile Flip-Flop Based on Majority-Decision Shared Writing," Proc. of 2016 International Conference on Solid State Devices and Materials (SSDM2016), pp. 79-80, Sep. 2016.
  • M. Natsui, A. Tamakoshi, T. Endoh, H. Ohno, and T. Hanyu, "Highly Reliable MTJ-Based Nonvolatile Logic-in-Memory LSI with Content-Aware Write Error Masking Scheme," Proc. of 2016 International Conference on Solid State Devices and Materials (SSDM2016), pp. 77-78, Sep. 2016.
  • A. Arash, F. Leduc-Primeau, N. Onizawa, T. Hanyu, and W. J. Gross, "VLSI Implementation of Deep Neural Networks Using Integral Stochastic Computing," Proc. 6th International Symposium on Turbo Codes & Iterative Information Processing, pp. 216-220, Sep. 2016.
  • D. Suzuki and T. Hanyu, "A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure," Proceeding of International Conference on Field-Programmable Logic and Applications (FPL), pp. 1-4, Aug. 2016.
  • M. Natsui, N. Sugaya, and T. Hanyu, "A Study of a Top-Down Error Correction Technique Using Recurrent-Neural-Network-Based Learning," Proc. 14th IEEE International New Circuits and Systems Conference (NEWCAS), June 2016.
  • N. Onizawa, and T. Hanyu, "Redundant STT-MTJ-Based Nonvolatile Flip-Flops for Low Write-Error-Rate Operations," Proc. 14th IEEE International New Circuits and Systems Conference (NEWCAS), pp. 1-4, June 2016.
  • M. Natsui, A. Tamakoshi, A. Mochizuki, H. Koike, H. Ohno, T. Endoh, and T. Hanyu, "Stochastic Behavior-Considered VLSI CAD Environment for MTJ/MOS-Hybrid Microprocessor Design," 2016 IEEE International Symposium on Circuits and Systems(ISCAS2016), pp. 1878-1881, May 2016.
  • S. Koshita, N. Onizawa, M. Abe, T. Hanyu, and M. Kawamata, "Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation," Proc. of the 46th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2016), pp. 223-228, May 2016.
  • N. Sugaya, M. Natsui, and T. Hanyu, "Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission," Proc. of the 46th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2016), pp. 72-77, May 2016.
  • D. Suzuki and T. Hanyu, "Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme," Proc. of the 46th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 5-10, May 2016.
  • N. Onizawa, S. Koshita, S. Sakamoto, M. Abe, M. Kawamata, and T. Hanyu, "Gammatone Filter Based on Stochastic Computation," Proc. 41st IEEE International Conference on Acoustic, Speech, and Signal Processing (ICASSP), pp. 1036-1040, Mar. 2016.

招待講演/招待講義

  • M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, "Towards Ultra Low-Power and Highly Dependable VLSI Computing Based on MTJ-Based Nonvolatile Logic-in-Memory Architecture," Proc. of BIT’s 6th Annual World Congress of Nano Science & Technology 2016 (Nano-S&T), Oct. 2016.
  • T. Hanyu, "Challenge of Spintronics-Based Nonvolatile Logic-in-Memory VLSI Architecture towards the IoE Era," 2016 Spintronics Workshop on LSI, p. 6, June 2016.
  • T. Hanyu, "Challenge of MOS/MTJ-Hybrid Nonvolatile VLSI Processor for IoE Applications," VLSI Technology Short Course 2016, No. 8, June 2016.


【2015年】

学術論文誌

  • N. Onizawa, D. Katagiri, K. Matsumiya, W. J. Gross, and T. Hanyu, "Gabor Filter Based on Stochastic Computation," IEEE Signal Processing Letters, Vol. 22, No. 9, pp. 1224-1228, Sep. 2015.
  • H. Jarollahi, V. Gripon, N. Onizawa, and W. J. Gross, "Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks," IEEE Trans. VLSI Syst., Vol. 23, No. 4, pp. 642-653, Apr. 2015.
  • H. Koike, T. Ohsawa, S. Miura, H. Honjo, S. Ikeda, T. Hanyu, H. Ohno, and T. Endoh, "Power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation," Japanese Journal of Applied Physics (JJAP), Vol. 54, No. 4, p. 04DE08, Apr. 2015.
  • D. Suzuki and T. Hanyu, "Nonvolatile Field-Programmable Gate Array Using 2-Transistor-1-Magnetic-Tunnel-Junction-Vell-Based Multi-Context Array for Power and Area Efficient Dynamically Reconfigurable Logic," Japanese Journal of Applied Physics (JJAP), Vol. 54, No. 4S, pp. 04DE01-1-04DE01-5, Mar. 2015.
  • M. Natsui, D. Suzuki, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, T. Sugibayashi, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, "Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction," IEEE Journal of Solid-State Circuits (JSSC), Vol. 50, No. 2, pp. 476-489, Feb. 2015.
  • D. Suzuki and T. Hanyu, "Magnetic-Tunnel-Junction Based Low-Energy Nonvolatile Flip-Flop Using An Area-Efficient Self-Terminated Write Driver," Journal of Applied Physics (JAP), Vol. 117, pp. 17B504-1-17B504-3, Jan. 2015.

国際会議(査読あり)

  • A. Mochizuki, N. Onizawa, A. Tamakoshi, and T. Hanyu, "Multiple-Event-Transient Soft-Error Gate-Level Simulator for Harsh Radiation Environments," Proceedings of IEEE TENCON 2015, No. 1658, Nov. 2015.
  • A. Mochizuki, N. Yube, and T. Hanyu, "Design of a Computational Nonvolatile RAM for a Greedy Energy-Efficient VLSI Processor," 41st Annual Conference of the IEEE Industrial Electronics Society (IECON2015), pp. 003283-003288, Nov. 2015.
  • K. Boga, N. Onizawa, F. L.-Primeau, K. Matsumiya, T. Hanyu, and W. Gross, "Stochastic Implementation of the Disparity Energy Model for Depth Perception," IEEE International Workshop on Signal Processing Systems (SiPS), Oct. 2015.
  • D. Suzuki and T. Hanyu, "Design of an MTJ-Based Nonvolatile Lookup Table Circuit Using an Energy-Efficient Single-Ended Logic-In-Memory Structure," Proc. IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 317-320, Aug. 2015.
  • N. Onizawa, S. Koshita, and T. Hanyu, "Scaled IIR Filter Based on Stochastic Computation," Proc. IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 297-300, Aug. 2015.
  • N. Onizawa, D. Katagiri, K. Matsumiya, W. J. Gross, and T. Hanyu, "Frequency-Flexible Stochastic Gabor Filter," Proc. 2015 IEEE International Conference on Digital Signal Processing (DSP), pp. 458-462, July 2015.
  • N. Onizawa, A. Mochizuki, A. Tamakoshi, and T. Hanyu, "A Sudden Power-Outage Resilient Nonvolatile Microprocessor for Immediate System Recovery," IEEE/ACM Int. Symp. Nanoscale Architectures (NANOARCH), pp. 39-44, July 2015.
  • D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, "Fabrication of a 3000-6-Input-LUTs Embedded and Block-Level Power-Gated Nonvolatile FPGA Chip Using p-MTJ-Based Logic-in-Memory Structure," Symp. VLSI Circuits Dig. Tech. Papers, pp. 172-173, June 2015.
  • S. Oosawa, T. Konishi, N. Onizawa, and T. Hanyu, "Design of an STT-MTJ Based True Random Number Generator Using Digitally Controlled Probability-Locked Loop," Proc. 13th IEEE International NEWCAS Conference, pp. 468-471, June 2015.
  • T. Hanyu, "Challenge of MOS/MTJ-Hybrid Integrated Circuits Based on Nonvolatile Logic-in-Memory Architecture," 2015 Spintronics Workshop on LSI, p. 7, June 2015.
  • D. Katagiri, N. Onizawa, and T. Hanyu, "Early-Stage Operation-Skipping Scheme for Low-Power Stochastic Image Processors," Proc. IEEE International Symposium on Multiple-Valued Logic (ISMVL 2015), pp. 109-114, May 2015.
  • T. Akutsu, M. Natsui, and T. Hanyu, "Write-Operation Frequency Reduction for Nonvolatile Logic LSI with a Short Break-Even Time," Proc. IEEE International Symposium on Multiple-Valued Logic (ISMVL 2015), pp. 152-157, May 2015.
  • T. Hanyu, D. Suzuki, N. Onizawa, S. Matsunaga, M. Natsui, and A. Mochizuki, "Spintronics-Based Nonvolatile Logic-in-Memory Architecture Towards an Ultra-Low-Power and Highly Reliable VLSI Computing Paradigm," Proc. Design Automation & Test in Europe (DATE), pp. 1006-1011, Mar. 2015.
  • T. Yoneda, M. Imai, Hiroshi Saito, T. Hanyu, K. Kise, and Y. Nakamura, "An NoC-based evaluation platform for safety-critical automotive applications," Proc. 2015 Feb 5 IEEE Asia-Pacific Conferrence on Circuits and Systems (APCCAS), pp. 679-682, Feb. 2015.

招待講演/招待講義

  • T. Hanyu, "Spintronics-Based Logic-in-Memory Architecture Towards Dark Silicon Era," International Workshop: Spintronics VLSI, Abstract, p. 9, Nov. 2015.
  • T. Hanyu, M. Natsui, D. Suzuki, A. Mochizuki, N. Onizawa, S. Ikeda, T. Endoh, and H. Ohno, "Challenge of MTJ-Based Nonvolatile Logic-in-Memory Architecture for Ultra Low-Power and Highly Dependable VLSI Computing," IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct. 2015.
  • T. Hanyu, "Nonvolatile Logic-in-Memory Architecture for Ultra-Low-Power VLSI Systems," ISSCC 2015, Forum 4, Feb. 2015.

書籍

  • T. Hanyu, "Challenge of Nonvolatile Logic LSI Using MTJ-Based Logic-in-Memory Architecture," in Spintronics-based Computing, Zhao, Weisheng, Prenat, Guillaume, Eds., pp. 159-177, Sep. 2015.


【2014年】

学術論文誌

  • H. Jarollahi, N. Onizawa, V. Gripon, N. Sakimura, T. Sugibayashi, T. Endoh, H. Ohno, and T. Hanyu, and W. J. Gross, "A Non-Volatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 4, No. 4, pp. 460-474, Dec. 2014.
  • D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu, "Cost-Efficient Self-Terminated Write Driver for Spin-Transfer-Torque RAM and Logic," IEEE Trans. Magn., Vol. 50, No. 11, pp. 3402104~1-3402104~4, Nov. 2014.
  • N. Onizawa and T. Hanyu, "Soft-Error Tolerant Transistor/Magnetic-Tunnel-Junction Hybrid Non-Volatile C-element," IEICE Electronics Express (ELEX), Vol. 11, No. 24, p. 20141017, Nov. 2014.
  • N. Onizawa, W. J. Gross, T. Hanyu, and V. C. Gaudet, "Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes: Algorithm and Simulation Model," IEICE Trans. Inf. and Syst., Vol. E97-D, No. 9, pp. 2286-2295, Sep. 2014.
  • A. Mochizuki, H. Shirahama, Y. Watanabe, and T. Hanyu, "Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip," IEICE Trans. Inf. and Syst., Vol. E97-D, No. 9, pp. 2304-2311, Sep. 2014.
  • N. Onizawa, W. J. Gross, T. Hanyu, and V. C. Gaudet, "Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model," Journal of Signal Processing Systems (JSPS), Vol. 76, No. 2, pp. 185-194, Aug. 2014.
  • D. Suzuki, N. Sakimura, M. Natsui, A. Mochizuki, T. Sugibayashi, T. Endoh, H. Ohno, and T. Hanyu, "A Compact Low-Power Nonvolatile Flip-Flop Using Domain-Wall-Motion-Device-Based Single-Ended Structure," IEICE Electronics Express (ELEX), Vol. 11, No. 13, pp. 20140296~1-20140296~11, June 2014.
  • N. Onizawa, A. Mochizuki, H. Shirahama, M. Imai, T. Yoneda, and T. Hanyu, "High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs," IEICE Trans. Inf. and Syst., Vol. E97-D, No. 6, pp. 1546-1556, June 2014.
  • T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, and T. Endoh, "Trend of tunnel magnetoresistance and variation in threshold voltage for keeping data load robustness of metal-oxide?semiconductor/magnetic tunnel junction hybrid latches," Journal of Applied Physics (JAP), Vol. 115, p. 17C728, May 2014.
  • N. Sakimura, R. Nebashi, M. Natsui, H. Ohno, T. Sugibayashi, and T. Hanyu, "Analysis of single-event upset of magnetic tunnel junction used in spintronic circuits caused by radiation-induced current," Journal of Applied Physics (JAP), Vol. 115, p. 17B748, May 2014.
  • S. Matsunaga, A. Mochizuki, N. Sakimura, R. Nebashi, T. Sugibayashi, T. Endoh, H. Ohno, and T. Hanyu, "Complementary 5T-4MTJ Nonvolatile TCAM Cell Circuit with Phase-Selective Parallel Writing Scheme," IEICE Electronics Express (ELEX), Vol. 11, No. 10, pp. 20140297~1-20140297~7, Apr. 2014.
  • H. Jarollahi, N. Onizawa, V. Gripon, and W. J. Gross, "Algorithm and Architecture of Fully-Parallel Associative Memories Based on Sparse Clustered Networks," Journal of Signal Processing Systems (JSPS), Vol. 76, No. 3, pp. 235-247, Apr. 2014.
  • N. Onizawa, S. Matsunaga, V. C. Gaudet, W. J. Gross, and T. Hanyu, "High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism," IEEE Trans. Circuits and Syst. I Reg. Papers, Vol. 61, No. 3, pp. 865-876, Mar. 2014.
  • N. Onizawa, A. Matsumoto, T. Funazaki, and T. Hanyu, "High-Throughput Compact Delay-Insensitive Asynchronous NoC Router," IEEE Trans. Computers, Vol. 63, No. 3, pp. 637-649, Mar. 2014.
  • D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, K. Kinoshita, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, "Design and Fabrication of a Perpendicular Magnetic Tunnel Junction Based Nonvolatile Programmable Switch Achieving 40% Less Area Using Shared-Control Transistor Structure," Journal of Applied Physics (JAP), Vol. 115, No. 17, pp. 17B742-1-17B742-3, Mar. 2014.
  • H. Koike, T. Ohsawa, S. Miura, H. Honjo, S. Ikeda, T. Hanyu, H. Ohno, and T. Endoh, "Wide operational margin capability of 1 kbit spin-transfer-torque memory array chip with 1-PMOS and 1-bottom-pin-magnetic-tunnel-junction type cell," Japanese Journal of Applied Physics, Vol. 53, No. 4S, p. 04ED13, Mar. 2014.
  • T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, and T. Endoh, "A two-transistor bootstrap type selective device for spin-transfer-torque magnetic tunnel junctions," Japanese Journal of Applied Physics (JJAP), Vol. 53, No. 4, p. 04ED03, Feb. 2014.
  • D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu, "Design and Evaluation of a 67% Area-Less 64-Bit Parallel Reconfigurable 6-Input Nonvolatile Logic Element Using Domain-Wall Motion Devices," Japanese Journal of Applied Physics (JJAP), Vol. 53, No. 4S, pp. 04EM03-1-04EM03-5, Feb. 2014.
  • S. Matsunaga, A. Mochizuki, T. Endoh, H. Ohno, and T. Hanyu, "Design of an Energy-Efficient 2T-2MTJ Nonvolatile TCAM Based on a Parallel-Serial-Combined Search Scheme," IEICE Electronics Express (ELEX), Vol. 11, No. 3, pp. 20131006-1-20131006-10, Jan. 2014.

国際会議(査読あり)

  • T. Hanyu, D. Suzuki, A. Mochizuki, M. Natsui, N. Onizawa, T. Sugibayashi, S. Ikeda, T. Endoh, and H. Ohno, "Challenge of MOS/MTJ-Hybrid Nonvolatile Logic-in-Memory Architecture in Dark-Silicon Era," IEEE International Electron Devices Meeting (IEDM) Technical Digest, pp. 28.2.1-28.2.3, Dec. 2014.
  • D. Suzuki and T. Hanyu, "MTJ-Based Low-Energy Nonvolatile Flip-Flop Using Area-Efficient Self-Terminated Write Driver," Abst. 59th Annual Conference on Magnetism & Magnetic Materials (MMM), p. 813, Nov. 2014.
  • A. Mochizuki, H. Shirahama, N. Onizawa, and T. Hanyu, "Highly Reliable Single-Ended Current-Mode Circuit for an Inter-Chip Asynchronous Communication Link," Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 683-686, Nov. 2014.
  • H. Jarollahi, N. Onizawa, T. Hanyu, and W. J. Gross, "Algorithm and Architecture for a Multiple-Field Context-Driven Search Engine Using Fully-Parallel Clustered Associative Memories," Proc. 2014 IEEE International Workshop on Signal Processing Systems (SIPS), pp. 133-138, Oct. 2014.
  • D. Suzuki and T. Hanyu, "Nonvolatile FPGA Using 2T-1MTJ-Cell-Based Multi-Context Array for Power and Area Efficient Dynamically Reconfigurable Logic," Ext. Abst. International Conference on Solid State Devices and Materials (SSDM), pp. 450-451, Sep. 2014.
  • N. Onizawa, D. Katagiri, W. J. Gross, and T. Hanyu, "Analog-to-Stochastic Converter Using Magnetic-Tunnel Junction Devices," Proc. IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pp. 59-64, July 2014.
  • H. Shirahama, A. Mochizuki, Y. Watanabe, and T. Hanyu, "Energy-Aware Current-Mode Inter-Chip Link for a Dependable GALS NoC Platform," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1865-1868, June 2014.
  • R. Nebashi, N. Sakimura, H. Honjo, A. Morioka, Y. Tsuji, K. Ishihara, K. Tokutome, S. Miura, S. Fukami, K. Kinoshita, T. Hanyu, T. Endoh, N. Kasai, H. Ohno, and T. Sugibayashi, "A Delay Circuit with 4-Terminal Magnetic-Random-Access-Memory Device for Power-Efficient Time-Domain Signal Processing," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1588-1591, June 2014.
  • M. Natsui and T. Hanyu, "Fabrication of a MTJ-Based Multilevel Resistor Towards Process-Variation-Resilient Logic LSI," Proc. 12th IEEE International NEWCAS Conference, pp. 468-471, June 2014.
  • N. Onizawa, S. Matsunaga, and T. Hanyu, "Design of a Soft-Error Tolerant 9-Transistor/6-Magnetic-Tunnel-Junction Hybrid Cell Based Nonvolatile TCAM," Proc. 12th IEEE International NEWCAS Conference, pp. 193-196, June 2014.
  • N. Onizawa, S. Matsunaga, and T. Hanyu, "A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure," 20th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 1-8, May 2014.(Best Paper Finalist)
  • D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu, "Optimally Self-Terminated Compact Switching Circuit Using Continuous Voltage Monitoring Achieving High Read Margin for STT MRAM and Logic," Abst. International Magnetics Conference (INTERMAG), pp. 2506-2507, May 2014.
  • M. Natsui and T. Hanyu, "Variation-Effect Analysis of MTJ-Based Multiple-Valued Programmable Resistors," Proc. 44th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 243-247, May 2014.
  • H. Jarollahi, N. Onizawa, T. Hanyu, and W. J. Gross, "Associative Memories Based on Multiple-Valued Sparse Clustered Networks," Proc. 44th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 208-213, May 2014.
  • N. Onizawa, S. Matsunaga, N. Sakimura, R. Nebashi, T. Sugibayashi, and T. Hanyu, "Soft-Delay-Error Evaluation in Content-Addressable Memory," Proc. 44th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 220-225, May 2014.
  • A. Mochizuki, H. Shirahama, and T. Hanyu, "Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-Chip Asynchronous Communication Link," Proc. 44th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 67-72, May 2014.
  • T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, and T. Endoh, "Studies on read-stability and write-ability of fast access STT-MRAMs," 2014 Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), p. 6839665, Apr. 2014.
  • N. Sakimura, Y. Tsuji, R. Nebashi, H. Honjo, A. Morioka, K. Ishihara, K. Kinoshita, S. Fukami, S. Miura, N. Kasai, T. Endoh, H. Ohno, T. Hanyu, and T. Sugibayashi, "A 90nm 20MHz Fully Nonvolatile Microcontroller for Standby-Power-Critical Applications," IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 184-185, Feb. 2014.

招待講演/招待講義

  • A. Mochizuki, M. Natsui, N. Sakimura, T. Sugibayashi, and T. Hanyu, "Challenge of Nonvolatile TCAM Design Automation," Booklet of the 23rd International Workshop on Post-Binary ULSI Systems, p. 1, May 2014.

書籍


【2013年】

学術論文誌

  • M. Natsui and T. Hanyu, "Design of Process-Variation-Resilient Analog Basic Components Using Magnetic-Tunnel-Junction Devices," Journal of Multiple-Valued Logic and Soft Computing, Vol. 21, No. 5-6, pp. 597-608, Dec. 2013.
  • T. Hanyu, "Challenge of MTJ-Based Nonvolatile Logic-in-Memory Architecture for Dark-Silicon Logic LSI," SPIN, Vol. 3, No. 4, pp. 1340014-1-1340014-8, Dec. 2013.
  • D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, K. Kinoshita, H. Sato, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, "Fabrication of a Magnetic Tunnel Junction-Based 240-Tile Nonvolatile Field-Programmable Gate Array Chip Skipping Wasted Write Operations for Greedy Power-Reduced Logic Applications," IEICE Electronics Express (ELEX), Vol. 10, No. 23, pp. 20130772-1-20130772-10, Nov. 2013.
  • N. Onizawa, A. Matsumoto, and T. Hanyu, "Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links," IEICE Trans. Inf. & Syst., Vol. E96D, No. 9, pp. 1952-1961, Sep. 2013.
  • T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Hanyu, H. Ohno and T. Endoh, "A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme," IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 6, pp. 1511-1520, June 2013.
  • 松本敦, 河野宇朗, 鬼沢直哉, 羽生貴弘, "制御情報共有化に基づく非同期細粒度パワーゲーティング技術とそのオンチップルータへの応用," 電子情報通信学会論文誌C, Vol. J96-C, No. 5, pp. 73-84, May 2013.
  • N. Onizawa, S. Matsunaga, V. C. Gaudet, W. J. Gross, and T. Hanyu, "High-Throughput CAM Based on a Synchronous Overlapped Search Scheme," IEICE Electronics Express (ELEX), Vol. 10, No. 7, pp. 20130148-1-20130148-9, Apr. 2013.
  • D. Suzuki, Y. Lin, M. Natsui, and T. Hanyu, "A 71%-Area-Reduced Six-Input Nonvolatile Lookup-Table Circuit Using a Three-Terminal Magnetic-Tunnel-Junction-Based Single-Ended Structure," Japanese Journal of Applied Physics (JJAP), Vol. 52, No. 4, pp. 04CM04-1-04CM04-6, Mar. 2013.

国際会議(査読あり)

  • D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, K. Kinoshita, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu, "Fabrication of a Perpendicular-MTJ-Based Compact Nonvolatile Programmable Switch Using Shared-Write-Control-Transistor Structure," Abst. 58th Annual Conference on Magnetism & Magnetic Materials (MMM), p. 233, Nov. 2013.
  • N. Onizawa, S. Matsunaga, V. C. Gaudet, W. J. Gross, and T. Hanyu, "Probabilistic Search Schemes for High-Speed Low-Power Content-Addressable Memories," Proc. International Conference on Analog VLSI Circuits, pp. 100-105, Oct. 2013.
  • D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu, "Design of a Three-Terminal MTJ-Based Nonvolatile Logic Element with a 2-ns 64-Bit-Parallel Reconfiguration Capability," Ext. Abst. International Conference on Solid State Devices and Materials (SSDM), pp. 386-387, Sep. 2013.
  • T. Hanyu, "Towards a Nonvolatile VLSI Processor Using MTJ/MOS-Hybrid Logic-in-Memory Architecture," Non-Volatile Memory Technology Symposium (NVMTS), D-2, Aug. 2013.(Invited Talk)
  • S. Matsunaga, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, T. Sugibayashi, S. Miura, H. Honjo, K. Kinoshita, H. Sato, S. Fukami, M. Natsui, A. Mochizuki, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, "Fabrication of a 99%-Energy-Less Nonvolatile Multi-Functional CAM Chip Using Hierarchical Power Gating for a Massively-Parallel Full-Text-Search Engine," Symposium on VLSI Circuits Digest of Technical Papers, pp. 106-107, June 2013.
  • T. Hanyu, Y. Watanabe, and A. Matsumoto, "Accurate and High-Speed Asynchronous Network-on-Chip Simulation Using Physical Wire-Delay Information," Proc. 43rd IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 266-271, May 2013.
  • N. Onizawa, W. J. Gross, T. Hanyu, and V. C. Gaudet, "Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating," 43rd IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 254-259, May 2013.
  • M. Natsui, K. Kashiuchi, and T. Hanyu, "Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications," Proc. 43rd IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 147-151, May 2013.
  • N. Onizawa, W. J. Gross, and T. Hanyu, "A Low-Energy Variation-Tolerant TCAM for Network Intrusion Detection Systems," Proc. 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 8-15, May 2013.
  • T. Hanyu, "Challenge of MTJ/MOS-Hybrid Logic-in-Memory Architecture for Nonvolatile VLSI Processor," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 117-120, May 2013.(Invited Talk)
  • M. Natsui, N. Sakimura, T. Sugibayashi, and T. Hanyu, "MTJ/MOS-Hybrid Logic-Circuit Design Flow for Nonvolatile Logic-in-Memory LSI," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 105-108, May 2013.
  • M. Natsui, D. Suzuki, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, T. Sugibayashi, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, "Nonvolatile Logic-in-Memory Array Processor in 90nm MTJ/MOS Achieving 75% Leakage Reduction Using Cycle-Based Power Gating," IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pp. 194-195, Feb. 2013.


【2012年】

学術論文誌

  • Masanori Natsui, Takashi Arimitsu, and Takahiro Hanyu, "Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique," Journal of Multiple-Valued Logic and Soft Computing, Vol. 19, No. 1-3, pp. 219-231, Sep. 2012.
  • Naoya Onizawa, Atsushi Matsumoto, and Takahiro Hanyu, "Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling," IEICE Transactions on Fundamentals, Vol. E95-A, No. 6, pp. 1018-1029, June 2012.
  • Daisuke Suzuki, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu, "Design of a Compact Nonvolatile Four-Input Logic Element Using a Magnetic-Tunnel-Junction and Metal-Oxide-Semiconductor Hybrid Structure," Japanese Journal of Applied Physics (JJAP), Vol. 51, No. 4, pp. 04DM02~1-04DM02~5, Apr. 2012.
  • Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu, "Design of a 270ps-Access 7T-2MTJ-Cell Nonvolatile Ternary Content-Addressable Memory," Journal of Applied Physics (JAP), Vol. 111, issue 7, pp. 07E336~1-07E336~3, Mar. 2012.
  • Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu, "Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory," Japanese Journal of Applied Physics (JJAP), Vol. 51, No. 2, pp. 02BM06~6-02BM06~11, Feb. 2012.
  • Daisuke Suzuki, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu, "Six-input Lookup Table Circuit with 62% Fewer Transistors Using Nonvolatile Logic-in-Memory Architecture with Series/Parallel-Connected Magnetic Tunnel Junctions," Journal of Applied Physics (JAP), Vol. 111, issue 7, pp. 07E318~1-07E318~3, Feb. 2012.

国際会議(査読あり)

  • Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, and Takahiro Hanyu, "Multi-Chip NoCs for Automotive Applications," Proc. 18th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), pp. 105-110, Nov. 2012.
  • Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, and Vincent C. Gaudet, "Clockless Stochastic Decoding of Low-Density Parity-Check Codes," Proc. Workshop on Signal Processing Systems (SiPS), pp. 143-148, Oct. 2012.
  • Daisuke Suzuki, Yuhui Lin, Masanori Natsui, and Takahiro Hanyu, "Design of Compact Nonvolatile Lookup-Table Circuit Using Three-Terminal Magnetic-Tunnel-Junction-Based Single-Ended Structure," Ext. Abst. International Conference on Solid State Devices and Materials (SSDM), pp. 392-393, Sep. 2012.
  • Daisuke Suzuki, Masanori Natsui, and Takahiro Hanyu, "Area-Efficient LUT Circuit Design Based on Asymmetry of MTJ's Current Switching for a Nonvolatile FPGA," Proc. 55th IEEE Midwest Symposium on Circuits and Systems (MWSCAS), pp. 334-337, Aug. 2012.
  • Luca Montesi, Zeljko Zilic, Takahiro Hanyu, and Daisuke Suzuki, "Building Blocks to Use in Innovative Non-Volatile FPGA Architecture Based on MTJs," Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 302-307, Aug. 2012.
  • Takahiro Hanyu, "Challenge of Nonvolatile Logic-in-Memory Architecture Towards Cool LSI Chips," 2012 Spintronics Workshop on LSI, p. 8, June 2012.
  • Shoun Matsunaga, Sadahiko Miura, Hiroaki Honjou, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu, "A 3.14 μm2 4T-2MTJ-Cell Fully Parallel TCAM Based on Nonvolatile Logic-in-Memory Architecture," Symposium on VLSI Circuits Digest of Technical Papers, pp. 44-45, June 2012.
  • Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjou, Keiichi Tokutome, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu, "1Mb 4T-2MTJ Nonvolatile STT-RAM for Embedded Memories Using 32b Fine-Grained Power Gating Technique with 1.0ns/200ps Wake-up/Power-off Times," Symposium on VLSI Circuits Digest of Technical Papers, pp. 46-47, June 2012.
  • Yukihide Tsuji, Ryusuke Nebashi, Noboru Sakimura, Ayuka Morioka, Hiroaki Honjo, Keiichi Tokutome, Sadahiko Miura, Tetsuhiro Suzuki, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, and Tadahiko Sugibayashi, "Spintronics Primitive Gate with High Error Correction Efficiency 6(Perror)2 for Logic-in Memory Architecture," Symposium on VLSI Technology Digest of Technical Papers, pp. 63-64, June 2012.
  • Tetsuo Endoh, Takashi Ohsawa, Hiroki Koike, Takahiro Hanyu, and Hideo Ohno, "Restructuring of Memory Hierarchy in Computing System with Spintronics-Based Technologies," Symposium on VLSI Circuits Digest of Technical Papers, pp. 89-90, June 2012.
  • Masanori Natsui and Takahiro Hanyu, "Scalable Serial-Configuration Scheme for MTJ/MOS-Hybrid Variation-Resilient VLSI System," Proc. 10th IEEE International NEWCAS Conference, pp. 97-100, June 2012.
  • Magdalena Sihotang, Shoun Matsunaga, and Takahiro Hanyu, "Fine-Grained Power-Gating Scheme of a Nonvolatile Logic-in-Memory Circuit for Low-Power Motion-Vector Extraction," Proc. 10th IEEE International NEWCAS Conference, pp. 485-488, June 2012.
  • Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, and Takahiro Hanyu, "High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism," Proc. International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 41-48, May 2012.
  • Atsushi Matsumoto, Naoya Onizawa, and Takahiro Hanyu, "Systematic Coding Schemes for Low-Power Multiple-Valued Current-Mode Asynchronous Communication Links," Proc. 42nd IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 13-18, May 2012.
  • Masanori Natsui, Takaaki Nagashima, and Takahiro Hanyu, "Process-Variation-Resilient OTA Using MTJ-Based Multi-Level Resistance Control," Proc. 42nd IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 214-219, May 2012.
  • Shoun Matsunaga and Takahiro Hanyu, "Quaternary 1T-2MTJ Cell Circuit for a High-Density and a High-Throughput Nonvolatile Bit-Serial CAM," Proc. 42nd IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 98-103, May 2012.
  • Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu, and Warren J. Gross, "Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes," 42nd IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 92-97, May 2012.
  • Youngkeun Kim, Masanori Natsui, and Takahiro Hanyu, "Variation-Resilient Current-Mode Logic Circuit Design Using MTJ Devices," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2705-2708, May 2012.
  • Takahiro Hanyu, "Nonvolatile Logic-in-Memory Architecture Using an MTJ/MOS-Hybrid Structure and Its Applications," Proc. IEEE COOL Chips XV, pp. 1-2, Apr. 2012.(Invited Talk)
  • Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu, "Implementation of a Perpendicular MTJ-Based Read-Disturb-Tolerant 2T-2R Nonvolatile TCAM Based on a Reversed Current Reading Scheme," Proc. Asia and South Pacific Design Automation Confrence (ASP-DAC), pp. 475-476, Jan. 2012.


【2011年】

学術論文誌

  • Naoya Onizawa, Vincent C. Gaudet, and Takahiro Hanyu, "Low-Energy Asynchronous Interleaver for Clockless Fully-Parallel LDPC Decoding," IEEE Trans. Circuits and Syst., Part I, Vol. 58, No. 8, pp. 1933-1943, Aug. 2011.
  • Satoru Hanzawa and Takahiro Hanyu, "Design of an 8-nsec 72-bit-Parallel-Search Content-Addressable Memory Using a Phase-Change Device," IEICE Trans. Electron., Vol. E94-C, No. 8, pp. 1302-1310, Aug. 2011.
  • Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu, "Design and Fabrication of a One-Transistor/One-Resistor Nonvolatile Binary Content-Addressable Memory Using Perpendicular Magnetic Tunnel Junction Devices with a Fine-Grained Power-Gating Scheme," Japanese Journal of Applied Physics (JJAP), Vol. 50, No. 6R, pp. 063004~1-036004~7, June 2011.

国際会議(査読あり)

  • Takao Kawano, Naoya Onizawa, Atushi Matsumoto, and Takahiro Hanyu, "Adjacent-State Monitoring Based Fine-Grained Power-Gating Scheme for a Low-Power Asynchronous Pipelined System," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2067-2070, May 2011.
  • Shoun Matsunaga, Akira Katsumata, Masanori Natsui, and Takahiro Hanyu, "Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme," 41st IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 99-104, May 2011.
  • Atsushi Matsumoto, Naoya Onizawa and Takahiro Hanyu, "Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links," Proc. 41th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 236-241, May 2011.
  • Naoya Onizawa, Atsushi Matsumoto, and Takahiro Hanyu, "Interconnect-Fault-Resilient Delay-Insensitive Asynchronous Communication Link Based on Current-Flow Monitoring," Proc. Design Automation & Test in Europe (DATE), pp. 776-781, Mar. 2011.

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