Welcome to Hanyu/Natsui Laboratory!
The research theme of this laboratory is ultra large scale semiconductor integrated circuit (VLSI) design technology based on a new way of thinking. In this laboratory, it aims to break down the limit of the VLSI system by extension of the conventional technology, by using not only the conventional silicon CMOS circuit method but also the circuit design, implementation method and system architecture of "new paradigm" actively utilizing new material / device characteristics. ->Continuation
We held Bohnenkai (end-of-year party). Pictures
Brainware engineering study seminer (Japanese) will be held.
Master's thesis preliminary examination meeting will be held.
Dr. Hanyu will participate in a joint meeting at The Hong Kong University of Science and Technology.
We attended the laboratory opposition Ekiden Convention. After that, we hold Oden party.
We held laboratory tour for jounier student.
Dr. Ng（University of Tronto）had an invited talk at Non-Volatile Memory Technology Symposium 2018 (NVMTS) at Sendai, Japan.
Dr. Matsuoka visited our laboratory.
We held Imoni party. Pictures
Creativity engineering training (Japanese) started for freshman in our laboratry.
Mr. Smithson (who is international student) went back to Canada.
We held a End-of-training-A party. Pictures
Mr. Smithson (from McGill university), Canada became a member of our laboratory for international student.カナダ，マギル大学のSean Smithson氏が来訪されました．
We held a Cherry-blossom viewing party. Pictures
Commencement ceremony was held. Pictures
Mr. Smithson (from McGill university) visited our laboratory.
We held a Mr. Katoh's farewell party. Pictures
Member's page was updated. Details
Mr. Katsumata (who is an alumnus) gave us New Year's card. Details (only for members)
Presentation / Results
Mr. Nishino had research presentation at 25th IEEE International Conference on Electronics Circuits and Systems (ICECS) at Bordeaux, France. Pictures
Dr. Hanyu gave a lecture at "IPS continuous seminor 2018 (Japanese)".
Mr. Suda, Mr. Nishino and Mr. Mukaida had short presentation and poster presentation at Brainware engineering study seminer (Japanese).
Dr. Hanyu had an invited talk at Non-Volatile Memory Technology Symposium 2018 (NVMTS) at Sendai, Japan.
Dr. Natsui had research presentation at S3S 2018 at San Francisco
An interim meeting of brain ware LSI project was held.
Dr. Onizawa and Mr. Nishino had research presentation at IEICE society conference 2018 at Kanazawa, Japan.
Dr. Hanyu had an invited talk and Dr. Natsui and Dr. Suzuki had research presentation at 2018 International Conference on Solid State Devices and Materials (SSDM) at Tokyo, Japan. Pictures
Dr. Suzuki and Mr. Chiba had research presentation at 2018 Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers at Morioka, Japan. Pictures
Dr. Hanyu had an invited talk at The 7th IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) at Hakodate, Japan.
Dr. Suzuki and Dr. Hanyu received "2017year Best Poster Award" in the presentation of "The 3rd 【ImPACT】 International Symposium on Spintronic Memory, Circuit and Storage"
Mr. Suda an Mr. Mukaida had research presentation at IEEE International Symposium on Multiple-Valued Logic (ISMVL) 2018 at Lintz, Austria. Pictures
Mr. Kato (who is an alumnus) received "The Young Scientist Presentation Award in IEICE Electronics Society Technical Committee on Integrated Circuits and Devices" at Design Gaia 2017. Details
Dr. Onizawa had research presentation at Emerging Technologies: Communications, Microsystems, Optoelectronics, Sensors (ETCMOS) 2018 Conference at Whistler, Canada.
Dr. Onizawa and Dr. Suzuki received "ECEI Young Excellence Research Award FY2017 (Japanese)". Deteils (Japanese)
Dr. Natsui had an invited talk at "China Semiconductor Technology International Conference (CSTIC) 2018 at Shanghai, China.
Dr. Natsui, Dr. Onizawa and Dr. Suzuki had research presentation at The 5th International Symposium on Brainware LSI at Sendai, Japan.
Dr. Suzuki, Mr. Suda, Mr. Nishino and Mr. Mukaida had research presentation at 31th multiple-valued logic and its application (Japanese) at Kanagawa, Japan. Pictures
Yoneda project debriefing session will be held.