A logic-in-memory VLSI architecture, in which small-capacity storage elements are distributed over a logic/arithmetic-circuit plane, has a potential advantage to perform highly parallel processing because the communnication between processing elements is localized.
In such a logic-in-memory VLSI architecture, the optimal scheduling and allocation methods to realize the highest-performance VLSI system under chip-area and/or power-dissipation constraints are disscussed.
   |
Title |
Journal |
Vol. |
No. |
Pages |
Year |
Authors |
1 |
NMOS Integrated Circuits for a Quaternary T-Gate (in Japanese) |
Trans. of IECE |
J67-D |
9 |
1064-1065 |
1984 |
M. Kameyama, T. Higuchi, M. Esashi and T. Hanyu |
2 |
Design and Implimentation of an NMOS Image Processor Based on Quaternary Logic (in Japanese) |
Trans. of IECE |
J69-D |
5 |
667-678 |
1986 |
T. Hanyu, M. Kameyama and T. Higuchi |
3 |
Design of a Quaternary Gate Array for High-Speed Pattern Matching (in Japanese) |
Trans. of IEICE |
J70-D |
2 |
493-496 |
1987 |
T. Hanyu, M. Kameyama and T. Higuchi |
4 |
Design and Implementation of Quaternary NMOS Integrated Circuits for Pipelined Image Processing |
IEEE J. Solid-State Circuits |
SC-22 |
1 |
20-27 |
1987 |
M. Kameyama, T. Hanyu and T. Higuchi |
5 |
Design of a Multiple-Valued Associative Memory (in Japanese) |
Trans. of IEICE |
J71-D |
8 |
1502-1510 |
1988 |
T. Hanyu and T. Higuchi |
6 |
High-Density Quaternary Logic Array Chip for Knowledge Information Processing Systems |
IEEE J. Solid-State Circuits |
SC-24 |
4 |
916-921 |
1989 |
T. Hanyu and T. Higuchi |
7 |
A Design of a High-Density Multi-Level Matching Array Chip for Associative Processing |
IEICE Trans. |
E74 |
4 |
918-928 |
1991 |
T. Hanyu, H. Ishii and T. Higuchi |
8 |
Dynamically Rule-Programmable VLSI Processor for Fully-Parallel Inference |
IEE Electronics Letters |
28 |
7 |
695-697 |
1992 |
T. Hanyu, K. Takeda and T. Higuchi |
9 |
Digit-Pipelined On-Chip Clique-Finding VLSI Processor for Real-Time 3-D Object Recognition |
IEE Electronics Letters |
28 |
8 |
722-724 |
1992 |
T. Hanyu, T. Kodama and T. Higuchi |
10 |
High-Speed Multiple-Valued Associative Memory Based on N-Ary-Tree Network (in Japanese) |
Trans. of IEICE |
J76-D-I |
2 |
54-62 |
1993 |
T. Hanyu and T. Higuchi |
11 |
Prospects of Multiple-Valued VLSI Processors |
IEICE Trans. on Electron. |
E76-C |
3 |
383-392 |
1993 |
T. Hanyu, M. Kameyama and T. Higuchi |
12 |
Rule-Programmable Multiple-Valued Matching VLSI Processor for Real-Time Rule-Based Systems |
IEICE Trans. on Electron. |
E76-C |
3 |
472-479 |
1993 |
T. Hanyu, K. Takeda and T. Higuchi |
13 |
3-D Object Recognition System Based on 2-D Chain Code Matching |
IEICE Trans. on Inf. & Syst. |
E76-A |
6 |
917-923 |
1993 |
T. Hanyu, S. Choi, M. Kameyama and T. Higuchi |
14 |
Multiple-Valued Programmable Logic Array Based on a Resonant-Tunneling Diode Model |
IEICE Trans. on Electron. |
E76-C |
7 |
1126-1132 |
1993 |
T. Hanyu, Y. Yabe and M. Kameyama |
15 |
A High-Density Multiple-Valued Content-Addressable Memory Based on One Transistor Cell |
IEICE Trans. on Electron. |
E76-C |
11 |
1649-1656 |
1993 |
S. Aragaki, T. Hanyu and T. Higuchi |
16 |
Low-Power 8-Valued Cellular Array VLSI for High-Speed Image Processing |
IEICE Trans. on Electronics |
E77-C |
7 |
1042-1048 |
1994 |
T. Hanyu, M. Kuwahara and T. Higuchi |
17 |
Design and Evaluation of a Current-Mode Multiple-Valued PLA Based on a Resonant Tunnelling Transistor Model |
IEE Proc. -Circuits Devices Syst. |
141 |
6 |
445-450 |
1994 |
X. Deng, T. Hanyu and M. Kameyama |
18 |
Prospects of Intelligent Integrated Systems toward Giga-Scale System-On-Chip (in Japanese) |
J. IEICE |
78 |
2 |
187-194 |
1993 |
M. Kameyama and T. Hanyu |
19 |
Functionally Separated, Multiple-Valued Content-Addressable Memory and Its Applications |
IEE Proc. -Circuits Devices Syst. |
142 |
3 |
165-172 |
1995 |
T. Hanyu, S. Aragaki and T. Higuchi |
20 |
Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate |
IEICE Trans. on Information and Systems |
E78-D |
8 |
951-958 |
1995 |
X. Deng, T. Hanyu and M. Kameyama |
21 |
Multiple-Valued Logic Network Using Quantum-Device-Oriented Superpass Gates and Its Minimisation |
IEE Proc. -Circuits Devices Syst. |
142 |
5 |
299-306 |
1995 |
X. Deng, T. Hanyu and M. Kameyama |
22 |
A 200 MHz Pipelined Multiplier Using 1.5 V-Supply Multiple-Valued MOS Current-Mode Circuits with Dual-Rail Source-Coupled Logic |
IEEE J. of Solid-State Circuits |
30 |
11 |
1239-1245 |
1995 |
T. Hanyu and M. Kameyama |
23 |
Design of a Rule-Based Highly-Safe Intelligent Vehicle Using a Content-Addressable Memory |
Trans. of the Society of Instrument and Control Engineers |
32 |
1 |
114-121 |
1996 |
T. Hanyu, S. Abe, M. Kameyama and T. Higuchi |
24 |
Synthesis of Multiple-Valued Logic Networks Based on Super Pass Gates |
Multiple-Valued Logic-International Journal |
1 |
   |
161-183 |
1996 |
X. Deng, T. Hanyu and M. Kameyama |
25 |
Design of a One-Transistor-Cell Multiple-Valued CAM |
IEEE J. of Solid-State Circuits |
SC-31 |
11 |
1669-1674 |
1996 |
T. Hanyu, N. Kanagawa and M. Kameyama |
26 |
Design and Evaluation of a Multiple-Valued Arithmetic Integrated Circuit Based on Differential Logic |
IEE Proc. -Circuits Devices Syst. |
143 |
6 |
331-336 |
1996 |
T. Hanyu, A. Mochizuki and M. Kameyama |
27 |
Non-Volatile One-Transistor-Cell Multiple-Valued CAM with a Digit-Parallel-Access Scheme and its Applications |
Computers Elect. Engng. |
23 |
6 |
407-414 |
1997 |
T. Hanyu, N. Kanagawa and M. Kameyama |
28 |
Design and Implementation of a Low-Power Multiple-Valued Current-Mode Integrated Circuit with Current-Source Control |
IEICE Trans. Electron. |
E80-C |
7 |
941-947 |
1997 |
T. Hanyu, S. Kazama and M. Kameyama |
29 |
Design and Evaluation of a 4-Valued Universal-Literal CAM for Cellular Logic Image Processing |
IEICE Trans. Electron. |
E80-C |
7 |
948-955 |
1997 |
T. Hanyu, M. Arakaki and M. Kameyama |
30 |
Design and Evaluation of a Digit-Parallel Multiple-Valued Content-Addressable Memory (in Japanese) |
Trans. IEICE D-I |
J81-D-I |
2 |
151-156 |
1998 |
T. Hanyu, K. Teranishi and M. Kameyama |
31 |
Optimal Design of a Current-Mode Deep-Submicron Multiple-Valued Integrated Circuit and its Application (in Japanese) |
Trans. IEICE D-I |
J81-D-I |
2 |
157-164 |
1998 |
T. Saito, T. Hanyu and M. Kameyama |
32 |
Multiple-Valued Logic-in-Memory VLSI Architecture Based on Floating-Gate-MOS Pass-Transistor Logic |
Trans. IEICE Trans. Electron. |
E82-C |
9 |
1662-1668 |
1999 |
T. Hanyu and M. Kameyama |
33 |
Self-Checking VLSI System Based on Dual-Rail Multiple-Valued Current-Mode Logic (in Japanese) |
Trans. IEICE C |
J83-C |
4 |
318-325 |
2000 |
T. Ike, T. Hanyu and M. Kameyama |
34 |
Asynchronous Current-Mode Multiple-Valued VLSI System Based on Two-Color Two-Rail Coding (in Japanese) |
Trans. IEICE C |
J83-C |
6 |
463-470 |
2000 |
T. Hanyu and M. Kameyama |
35 |
Logic-in-Memory VLSI Using Ferroelectric Devices and Its Application (in Japanese) |
Trans. IEICE C-II |
J83-C |
8 |
749-756 |
2000 |
H. Kimura, T. Hanyu and M. Kameyama |
36 |
Design of a Parallel VLSI Processor for Road Extraction Based on Logic-in-Memory Architecture (in Japanese) |
Trans. SICE |
36 |
11 |
1009-1018 |
2000 |
T. Kudoh, T. Hanyu and M. Kameyama |
37 |
Arithmetic-Oriented Logic-in-Memory VLSI Using Floating-Gate MOS Transistors |
Multiple-Valued Logic-International Journal |
8 |
1 |
33-51 |
2002 |
S. Kaeriyama, T. Hanyu and M. Kameyama |
38 |
Logic-in-Memory VLSI for Fully Parallel Nearest Pattern Matching Based on Floating-Gate MOS Pass-Transistor Logic |
Multiple-Valued Logic-International Journal |
   |
   |
   |
   |
T. Hanyu, S. Kaeriyama and M. Kameyama |
39 |
Dynamic-Storage-Based Logic-in-Memory Circuit and Its Application to a Fine-Grain Pipelined System |
IEICE Trans. on Electronics |
E85-C |
2 |
288-296 |
2002 |
H. Kimura, T. Hanyu and M. Kameyama |
40 |
Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit |
IEICE Trans. on Electronics |
E85-C |
10 |
1814-1823 |
2002 |
H. Kimura, T. Hanyu and M. Kameyama |
41 |
Multiple-Valued Logic-in-Memory VLSI Using MFSFETs and Its Applications |
Journal of Multiple-Valued Logic & Soft Computing |
9 |
1 |
23-42 |
2003 |
H. Kimura, T. Hanyu and M. Kameyama |
42 |
Optimal Design of a Dual-Rail Multiple-Valued Current-Mode Integrated Circuit Based on Voltage Swing Minimization |
Journal of Multiple-Valued Logic & Soft Computing |
9 |
1 |
5-21 |
2003 |
T. Ike, T. Hanyu and M. Kameyama |
42 |
Design of Ferroelectric-Based Logic-in-Memory VLSI (Japanese) |
IEICE-C |
J86-C |
8 |
886-893 |
2003 |
H. Kimura, T. Hanyu, M. Kameyama, T. Fujimori, T. Nakamura, and H. Takasu |
43 |
Low-Power Multiple-Valued Current-Mode Logic Using Substrate Bias Control |
IEICE Trans. on Electronics |
E87-C |
4 |
582-588 |
2004 |
A. Mochizuki and T. Hanyu |
44 |
Asynchronous Data Transfer Scheme Based on Simultaneous Control in a Bidirectional Way and Its VLSI Design (Japanese) |
IEICE-C |
J87-C |
5 |
459-468 |
2004 |
T. Takahashi, T. Hanyu, and M. Kameyama |
45 |
Complementary Ferroelectric-Capacitor Logic for Low-Power Logic- in-Memory VLSI |
IEEE Journal of Solid-State Circuits |
39 |
6 |
919-926 |
2004 |
H. Kimura, T. Hanyu, M. Kameyama, Y. Fujimori, T. Nakamura and H. Takasu |
46 |
Low-Power Motion-Vector Detection VLSI Processor Based on Pass-Gate Logic with Dynamic Supply-Voltage/Clock-Frequency Scaling |
IEICE Trans. on Electronics |
E87-C |
11 |
1876-1883 |
2004 |
A. Mochizuki, D. Nishinohara and T. Hanyu |
47 |
Dynamically Function-Programmable Bus Architecture for High- Throughput Intra-Chip Data Transfer |
IEICE Trans. on Electronics |
E87-C |
11 |
1915-1922 |
2004 |
A. Mochizuki, T. Takeuchi and T. Hanyu |
48 |
Differential Operation Oriented Multiple-Valued Encoding and Circuit Realization for Asynchronous Data Transfer |
IEICE Trans. on Electronics |
E87-C |
11 |
1928-1934 |
2004 |
T. Takahashi, N. Onizawa and T. Hanyu |
49 |
Multiple-Valued Logic as a New Computing Paradigm -A Brief Survey of Higuchi's Research on Multiple-Valued Logic- |
Journal of Multiple-Valued Logic and Soft Computing (Invited Paper) |
11 |
5-6 |
407-436 |
2005 |
Michitaka Kameyama, Takahiro Hanyu and Takafumi Aoki |
50 |
Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic |
Journal of Multiple-Valued Logic and Soft Computing |
11 |
5-6 |
481-498 |
2005 |
A. Mochizuki, T. Hanyu, and M. Kameyama |
51 |
Control Signal Multiplexing Based Asynchronous Data Transfer Scheme Using Multiple-Valued Bidirectional Current-Mode Circuits |
Journal of Multiple-Valued Logic and Soft Computing |
11 |
5-6 |
499-518 |
2005 |
T. Takahashi and T. Hanyu |
52 |
Logic-in-Memory VLSI for Fully Parallel Nearest Pattern Matching Based on Floating-Gate MOS Pass-Transistor Logic |
Multiple-Valued Logic-International Journal |
11 |
5-6 |
619-632 |
2005 |
T. Hanyu, S. Kaeriyama and M. Kameyama |
53 |
TMR-Based Logic-in-Memory Circuit for Low-Power VLSI |
IEICE Transactions on Fundamentals |
E88-A |
6 |
1408-1415 |
2005 |
A. Mochizuki, H. Kimura, M. Ibuki, and T. Hanyu |
54 |
Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic |
IEICE Trans. on Electronics |
E89-C |
11 |
1591-1597 |
2006 |
N. Onizawa and T. Hanyu |
55 |
Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing |
IEICE Trans. on Electronics |
E89-C |
11 |
1598-1604 |
2006 |
T. Takahashi and T. Hanyu |
56 |
Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic |
IEICE Trans. on Electronics |
E89-C |
11 |
1575-1580 |
2006 |
A. Mochizuki, H. Shirahama, and T. Hanyu |
57 |
Design and Evaluation of a 54x54-bit Multiplier Based on Differential-Pair Circuitry |
IEICE Trans. on Electronics |
E90-C |
4 |
683-691 |
2007 |
A. Mochizuki, H. Shirahama, and T. Hanyu |
58 |
Magnetic Tunnel Junctions for Spintronic Memories and Beyond (Invited Paper) |
IEEE Transactions on Electron Devices |
54 |
5 |
991-1002 |
2007 |
S. Ikeda, J. Hayakawa, Y. M. Lee, F. Matsukura, Y. Ohno, T. Hanyu, and H. Ohno |
59 |
Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling |
IEICE Trans. Electronics |
E91-C |
4 |
581-588 |
2008 |
K. Mizusawa, N. Onizawa, and T. Hanyu |
60 |
Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation |
IEICE Trans. Electronics |
E91-C |
4 |
589-594 |
2008 |
M. Miura and T. Hanyu |
61 |
Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions |
Applied Physics Express (APEX) |
1 |
9 |
09130-1~091301-3 |
2008 |
S. Matsunaga, J. Hayakawa, S. Ikeda, K. Miura, H. Hasegawa, T. Endoh, H. Ohno, and T. Hanyu |
62 |
Standby-Power-Free Compact Ternary Content-Addressable Memory Cell Chip Using Magnetic Tunnel Junction Devices |
Applied Physics Express (APEX) |
2 |
2 |
023004-1~023004-3 |
2009 |
S. Matsunaga, K. Hiyama, A. Matsumoto, S. Ikeda, H. Hasegawa, K. Miura, J. Hayakawa, T. Endoh, H. Ohno, and T. Hanyu |
63 |
Design of a Lookup Table Circuit Based on TMR Logic and Its Application to an Immediate Wake-Upable FPGA (Japanese) |
IEICE-C |
J92-C |
7 |
233-240 |
2009 |
D. Suzuki, M. Natsui, and T. Hanyu |
64 |
High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving |
IEICE Trans. Electronics |
E92-C |
6 |
867-874 |
2009 |
N. Onizawa, T. Hanyu, and V. C. Gaudet |
65 |
Design of High-Throughput Fully-Parallel LDPC Decoders Based on Wire Partitioning |
IEEE Transactions on VLSI |
18 |
* |
***-*** |
2010 |
N. Onizawa, T. Hanyu, and V. C. Gaudet |
66 |
Design of Threshold-Variation-Aware Multiple-Valued Current-Mode Circuit Using TMR Devices (Japanese) |
IEICE-D |
J93-D |
1 |
10-19 |
2010 |
A. Hirosaki, A. Matsumoto, T. Hanyu |
66 |
Fine-Grained Power-Gating Scheme of a Metal-Oxide-Semiconductor and Magnetic-Tunnel-Junction-Hybrid Bit-Serial Ternary Content-Addressable Memory |
Japanese Journal of Applied Physics (JJAP) |
49 |
** |
***-*** |
2010 |
S. Matsunaga, M. Natsui, K. Hiyama, T. Endoh, H. Ohno, and T. Hanyu |
   |
Title |
Journal |
Vol. |
Pages |
Year |
Authors |
1 |
An NMOS Pipelined Image Processor Using Quaternary Logic |
IEEE Int. Solid-State Circuits Conf. |
32 |
86-87 |
1985 |
M. Kameyama, T. Hanyu, M. Esashi and T. Higuchi |
2 |
Implementation of Quaternary NMOS Integrated Circuits for Pipelined Image Processing |
IEEE Int. Symp. on Multiple-Valued Logic |
15 |
226-232 |
1985 |
M. Kameyama, T. Hanyu, M. Esashi, T. Higuchi and T. Ito |
3 |
Quaternary Gate Array for Pattern Matching and its Application to Knowledge Information Processing System |
IEEE Int. Symp. on Multiple-Valued Logic |
17 |
181-187 |
1987 |
T. Hanyu, M. Kameyama and T. Higuchi |
4 |
Design of a Highly Parallel AI Processor Using New Multiple-Valued MOS Devices |
IEEE Int. Symp. on Multiple-Valued Logic |
18 |
300-306 |
1988 |
T. Hanyu and T. Higuchi |
5 |
High-Density Quaternary Logic Array Chip for Knowledge Information Processing Systems |
Symp. on VLSI Circuits |
3 |
29-30 |
1988 |
T. Hanyu and T. Higuchi |
6 |
Design of a High-Density Multiple-Valued Content-Addressable Memory Based on Floating-Gate MOS Devices |
IEEE Int. Symp. on Multiple-Valued Logic |
20 |
18-23 |
1990 |
T. Hanyu and T. Higuchi |
7 |
A Multiple-Valued Logic Array VLSI Based on Two-Transistor Delta Literal Circuit and Its Application to Real-Time Reasoning Systems |
IEEE Int. Symp. on Multiple-Valued Logic |
21 |
16-23 |
1991 |
T. Hanyu, Y. Kojima and T. Higuchi |
8 |
A Floating-Gate-MOS-Based Multiple-Valued Associative Memory |
IEEE Int. Symp. on Multiple-Valued Logic |
21 |
24-31 |
1991 |
T. Hanyu and T. Higuchi |
9 |
Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based Systems |
IEEE Int. Symp. on Multiple-Valued Logic |
22 |
274-281 |
1992 |
T. Hanyu, K. Takeda and T. Higuchi |
10 |
VLSI-Oriented 3-D Object Recognition Algorithm Based on Chain Code Matching |
Joint Technical Conf. on Circuits/Systems, Computers and Communications |
   |
36-40 |
1992 |
S. Choi, T. Hanyu, M. Kameyama and T.Higuchi |
11 |
200-Vertex On-Chip Clique-Finding VLSI Processor for Real-Time 3-D Object Recognition |
IEEE Int. Conf. on Industrial, Electronics, Control, Instrumentation and Automation |
3 |
1379-1384 |
1992 |
T. Hanyu, T. Kodama and T. Higuchi |
12 |
Beyond-Binary Circuits for Signal Processing |
IEEE Int. Solid-State Circuits Conf./TD>
| 36 |
134-135,277 |
1993 |
T. Hanyu, M. Kameyama and T. Higuchi/TD>
|
13 |
A Multiple-Valued Content-Addressable Memory Using Logic-Value Conversion and Threshold Functions |
IEEE Int. Symp. on Multiple-Valued Logic |
23 |
170-175 |
1993 |
S. Aragaki, T. Hanyu and T. Higuchi |
14 |
Prospects of Multiple-Valued Associative VLSI Processors |
IEEE Midwest Symposium on Circuits and Systems |
36 |
1484-1488 |
1993 |
T. Hanyu and M. Kameyama |
15 |
Design of a Low-Power Multiple-Valued Cellular Array Using Dynamic Circuits and Its Application to Image Processing |
IEEE Int. Workshop on Intelligent Signal Processing and Communication Systems |
   |
309-314 |
1993 |
T. Hanyu, M. Kuwahara and T. Higuchi |
16 |
Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic |
IEEE Int. Symp. on Multiple-Valued Logic |
24 |
19-26 |
1994 |
T. Hanyu, A. Mochizuki and M. Kameyama |
17 |
Rule-Based Highly-Safe Intelligent Vehicle Using a New Content-Addressable Memory |
IEEE Proc. of the Intelligent Vehicles Symposium |
   |
143-148 |
1994 |
M. Hariyama, T. Hanyu and M. Kameyama |
18 |
Rule-Based Highly-Safe Intelligent Vehicle Using a New Content-Addressable Memory |
IEEE Proc. of the Intelligent Vehicles Symposium |
   |
467-472 |
1994 |
T. Hanyu, S. Abe, M. Kameyama and T. Higuchi |
19 |
A 1.5V-Supply 200MHz Pipelined Multiplier Using Multiple-Valued Current-Mode MOS Differntial Logic Circuits |
IEEE Int. Solid-State Circuits Conf. |
38 |
314-386 |
1995 |
T. Hanyu, A. Mochizuki and M. Kameyama |
20 |
Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. |
IEEE Int. Symp. on Multiple-Valued Logic |
25 |
64-69 |
1995 |
T. Hanyu, A. Mochizuki and M. Kameyama |
21 |
Quantum Device Model Based Super Pass Gate for Multiple-Valued Digital Systems |
IEEE Int. Symp. on Multiple-Valued Logic |
25 |
92-97 |
1995 |
X. Deng, T. Hanyu and M. Kameyama |
22 |
On-Chip Hardware Accelerator for Model-Based 3-D Instrumentation Using Run-Length Matching |
IEEE Int. Conf. on Industrial Electronics, Control, and Instrumentation |
21 |
1319-1323 |
1995 |
M. Kamoshida, T. Hanyu and M. Kameyama |
23 |
One-Transistor-Cell Multiple-Valued CAM for a Collision Detection VLSI Processor |
IEEE Int. Solid-State Circuits Conf. |
39 |
264-265 |
1996 |
T. Hanyu, N. Kanagawa and M. Kameyama |
24 |
A Multiple-Valued Ferroelectric Content-Addressable Memory |
IEEE Int. Symp. on Multiple-Valued Logic |
26 |
74-79 |
1996 |
A. Sheikholeslami, P. G. Gulak and T. Hanyu |
25 |
Quaternary Universal-Literal CAM for Cellular Logic Image Processing |
IEEE Int. Symp. on Multiple-Valued Logic |
26 |
224-229 |
1996 |
T. Hanyu, M. Arakaki and M. Kameyama |
26 |
Non-Volatile One-Transistor-Cell CAM and its Applications |
Int. Conf. on Soft Computing |
4 |
101-104 |
1996 |
T. Hanyu, N. Kanagawa and M. Kameyama |
27 |
Low-Power Multiple-Valued Current-Mode Integrated Circuit with Current-Source Control and its Application |
Proc. Asia and South Pacific Design Automation Conf |
   |
413-418 |
1997 |
T. Hanyu, S. Kazama and M. Kameyama |
28 |
2-Transistor-Cell 4-Valued Universal-Literal CAM for a Cellular Logic Image Processor |
IEEE Int. Solid-State Circuits Conf. |
40 |
46-47 |
1997 |
T. Hanyu, M. Arakaki and M. Kameyama |
29 |
One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing |
IEEE Int. Symp. on Multiple-Valued Logic |
27 |
175-180 |
1997 |
T. Hanyu, M. Arakaki and M. Kameyama |
30 |
Multiple-Valued Logic-in-Memory VLSI Based on a Floating-Gate-MOS Pass-Transistor Network |
IEEE Int. Solid-State Circuits Conf. |
41 |
194-195 |
1998 |
T. Hanyu, K. Teranishi and M. Kameyama |
31 |
Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic |
IEEE Int. Symp. on Multiple-Valued Logic |
28 |
134-139 |
1998 |
T. Hanyu, T. Saito and M. Kameyama |
32 |
Multiple-Valued Floating-Gate-MOS Pass Logic and Its Application to Logic-in-Memory VLSI |
IEEE Int. Symp. on Multiple-Valued Logic |
28 |
270-275 |
1998 |
T. Hanyu, K. Teranishi and M. Kameyama |
33 |
Innovation of Intelligent Integrated System Architecture |
Int. Symp. on Future of Intellectual Integrated Electronics |
   |
231-247 |
1999 |
M. Kameyama, T. Hanyu and M. Hariyama |
34 |
Multiple-Valued Logic-in-Memory VLSI and Its Applications |
Int. Symp. on Future of Intellectual Integrated Electronics |
   |
271-281 |
1999 |
T. Hanyu and M. Kameyama |
35 |
Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs |
IEEE Int. Symp. on Multiple-Valued Logic |
29 |
30-35 |
1999 |
T. Hanyu, H. Kimura and M. Kameyama |
36 |
Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic |
IEEE Int. Symp. on Multiple-Valued Logic |
29 |
275-279 |
1999 |
T. Hanyu, T. Ike and M. Kameyama |
37 |
Design of Multiple-Valued Logic-in-Memory VLSI Based on Linear Summation |
Korea-Japan Joint Symposium on Multiple-Valued Logic |
1 |
211-218 |
1999 |
S. Kaeriyama, T. Hanyu and M. Kameyama |
38 |
Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels |
IEEE Int. Symp. on Multiple-Valued Logic |
30 |
382-387 |
2000 |
T. Hanyu, T. Ike and M. Kameyama |
39 |
DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage |
IEEE Int. Symp. on Multiple-Valued Logic |
30 |
423-429 |
2000 |
T. Hanyu, H. Kimura and M. Kameyama |
40 |
Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic |
IEEE Int. Symp. on Multiple-Valued Logic |
30 |
438-443 |
2000 |
S. Kaeriyama, T. Hanyu and M. Kameyama |
41 |
Integration of Asynchronous and Self-Checking Multiple-Valued Current-Mode Circuits Based on Dual-Rail Differential Logic |
Pacific Rim International Symposium on Dependable Computing |
   |
27-33 |
2001 |
T. Hanyu, T. Ike and M. Kameyama |
42 |
Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources |
IEEE International Symposium on Multiple-Valued Logic |
31 |
21-26 |
2001 |
T. Ike , T. Hanyu and M. Kameyama |
43 |
Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits |
IEEE International Symposium on Multiple-Valued Logic |
31 |
167-172 |
2001 |
T. Hanyu, M. Kameyama, K. Shimabukuro and C. Zukeran |
44 |
Ferroelectric-Based Functional Pass-Gate for Fine-Grain Pipelined VLSI Computation |
IEEE Int. Solid-State Circuits Conf |
   |
208-209 |
2002 |
T. Hanyu, H. Kimura, M. Kameyama, Y. Fujimori, T. Nakamura and H. Takasu |
45 |
Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition |
IEEE International Symposium on Multiple-Valued Logic |
32 |
161-166 |
2002 |
H.Kimura, T.Hanyu and M.Kameyama |
46 |
Fully Source-Coupled Logic Based Multiple-Valued VLSI |
IEEE International Symposium on Multiple-Valued Logic |
32 |
270-275 |
2002 |
T. Ike, T. Hanyu, and M. Kameyama |
47 |
Ferroelectric-Based Functional Pass-Gate for Low-Power VLSI |
IEEE Sympsium on VLSI Circuits |
   |
196-199 |
2002 |
H.Kimura, T.Hanyu, M.Kameyama, Y.Fujimori, T.Nakamura and H.Takasu |
48 |
Complementary Ferroelectric-Capacitor Logic for Low-Power Logic-in-Memory VLSI |
IEEE Int. Solid-State Circuits Conf |
   |
160-161 |
2003 |
H.Kimura, T.Hanyu, M.Kameyama, Y.Fujimori, T.Nakamura and H.Takasu |
49 |
Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current-Mode Logic |
IEEE International Symposium on Multiple-Valued Logic |
33 |
99-104 |
2003 |
T. Hanyu, T. Takahashi, and M. Kameyama |
50 |
Multiple-Valued Dynamic Source-Coupled Logic. |
IEEE International Symposium on Multiple-Valued Logic |
33 |
207-212 |
2003 |
T. Hanyu, A. Mochizuki and M. Kameyama |