Achievement

[2018]

Journal Papers

J.-P. Diguet, J. Sepulveda, N. Onizawa, M. Rizk, A. Baghdadi, and T. Hanyu, "Networked Power-gated MRAMs for Memory-Based Computing TVLSI-00640-2017.R2,"IEEE Transactions on Very Large Scale Integration (VLSI) Systems (accepted), 2018.
W. Gross, N. Onizawa, K. Matsumiya, and T. Hanyu, "Application of Stochastic Computing in Brainware," Nonlinear Theory and Its Applications (NOLTA) (accepted), Oct. 2018.
N. Onizawa, S. Koshita, S. Sakamoto, M. Kawamata, and T. Hanyu, "An Area/Power-Aware 32-Channel Compressive Gammachirp Filterbank Chip Based on Hybrid Stochastic/Binary Computation,"Nonlinear Theory and Its Applications (NOLTA) (accepted) ,Oct. 2018.
N. Onizawa, D. Katagiri, K. Matsumiya, W. J. Gross, T. Hanyu, "An Accuracy/Energy-Flexible Configurable Gabor-Filter Chip Based on Stochastic Computation with Dynamic Voltage-Frequency-Length Scaling," IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) (accepted), 2018.
D. Suzuki and T. Hanyu, "Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting," Japanese Journal of Applied Physics (JJAP), vol. 57, no. 4S, pp. 04FE09-1~4, Mar. 2018.
M. Natsui and T. Hanyu, "Design of a memory-access controller with 3.71-times-enhanced energy efficiency for Internet-of-Things-oriented nonvolatile microcontroller unit," Japanese Journal of Applied Physics (JJAP), Vol. 57, No. 4S, pp. 04FN03-1~5, Feb. 2018.

Peer-Reviewed International Conference Papers

M. Natsui, T. Chiba, and T. Hanyu, "MTJ-Based Nonvolatile Ternary Logic Gate for Quantized Convolutional Neural Networks," IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S) (accepted), Oct. 2018.
D. Suzuki and T. Hanyu, "A High-Read-Margin MTJ-Based Fracturable Lookup Table Circuit Using a Series-NMOS-Resistance-Reduced Logic-in-Memory Structure," Extended Abstracts of 2018 International Conference on Solid State Devices and Materials (SSDM2018) (accepted), Tokyo, Sep. 2018.
M. Natsui, T. Chiba, and T. Hanyu, "MTJ-Based Nonvolatile Logic Gate for Binarized Convolutional Neural Networks and Its Impact," Extended Abstracts of 2018 International Conference on Solid State Devices and Materials (SSDM2018) (accepted), Tokyo, Sep. 2018.
S. Mukaida, N. Onizawa, and T. Hanyu, Proceedings of the 48th International Symposium on Multiple-Valued Logic (ISMVL), pp. 156-161, May 2018.

H. Suda, M. Natsui, and T. Hanyu, "Systematic Intrusion Detection Technique for an In-Vehicle Network Based on Time-Series Feature Extraction," Proceedings of the 48th International Symposium on Multiple-Valued Logic (ISMVL), pp. 56-61, May 2018.
S. Koshita, N. Onizawa, T. Hanyu, and M. Kawamata, "High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure," Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2018.
M. Imai, N. Onizawa, T. Hanyu, T. Yoneda, "Minimum Power Supply Asynchronous Circuits for Re-initialization Free Computing," Proc. The 21st Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2018), pp. 283-288, Mar. 2018.
D. Suzuki, T. Hanyu, "Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA," 26th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2018), pp. 291, Feb. 2018.

Invited Speeches/Invited Tutorials

T. Hanyu, "Prospects of Nonvolatile Logic LSI Using MTJ/MOS-Hybrid Circuitry and Its Application," Extended Abstracts of 2018 International Conference on Solid State Devices and Materials (SSDM2018) , Tokyo, Sep. 2018.(invited)
T. Hanyu, T. Endoh, D. Suzuki, M. Natsui, and H. Ohno, "Impact of an MTJ-based logic LSI and its possibility," Proc. of the 7th IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) (accepted), Aug. 2018.
M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, "MTJ-Based Nonvolatile Logic LSI for Ultra Low-Power and Highly Dependable Computing," China Semiconductor Technology International Conference (CSTIC), pp. 1-54, Mar. 2018.

Books

H. Ohno, T. Endoh, T. Hanyu, Y. Ando and S. Ikeda, "Spin-transfer-torque magnetoresistive random access memory (STT-MRAM)," in Chapter 12 of "Advances in Non-volatile Memory and Storage Technology," edited by Yoshio Nishi, *** 2018 (to appear).

[2017]

Journal Papers

N. Onizawa, S. Koshita, S. Sakamoto, M. Abe, M. Kawamata, and T. Hanyu, "Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, No. 10, pp. 2724-2735, Oct. 2017.
A. Ardakani, F. Leduc-Primeau, N. Onizawa, T. Hanyu, and W. J. Gross, "VLSI Implementation of Deep Neural Networks Using Integral Stochastic Computing," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, No. 10, pp. 2688-2699, Oct. 2017.
D. Suzuki and T. Hanyu, "Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme," IEICE Trans. Inf. & Syst., Vol.E100-D, No.8, pp.1618-1624, Aug. 2017.
S. Koshita, N. Onizawa, M. Abe, T. Hanyu, and M. Kawamata, "High-Accuracy and Area-Efficient Stochastic FIR Digital Filters Based on Hybrid Computation," IEICE Trans. Inf. & Syst., Vol.E100-D, No.8, p.1592-1602, Aug. 2017.
N. Onizawa, A. Tamakoshi and T. Hanyu, "Evaluation of reinitialization-free nonvolatile computer systems for energy-harvesting Internet of things applications," Japanese Journal of Applied Physics (JJAP), Vol.56, No.8, pp.0802B7-1~0802B7-7, Jul. 2017.
N. Onizawa, A. Mochizuki, A. Tamakoshi, and T. Hanyu, "Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors," IEEE Transactions on Emerging Topics in Computing (TETC), vol. 5, No. 2, pp. 151-163, Apr.-Jun. 2017.
N. Onizawa and T. Hanyu, "Soft/Write-Error Resilient CMOS/MTJ Nonvolatile Flip-Flop Based on Majority-Decision Shared Writing," Japanese Journal of Applied Physics (JJAP), vol. 56, No. 4S, pp.04CF12~1-6, Mar. 2017.
M. Natsui, A. Tamakoshi, T. Endoh, H. Ohno, and T. Hanyu, "Fabrication of an MTJ-Based Nonvolatile Logic-in-Memory LSI with Content-Aware Write Error Masking Scheme Achieving 92% Storage Capacity and 79% Power Reduction," Japanese Journal of Applied Physics (JJAP), vol. 56, No. 4S, pp. 04CN01~-1-5, Mar. 2017.
D. Suzuki and T. Hanyu, "Design of a Low-Power Nonvolatile Flip-Flop Using 3-Terminal Magnetic-Tunnel-Junction-Based Self-Terminated Mechanism," Japanese Journal of Applied Physics (JJAP), vol. 56, No. 4S, pp. 04CN06~1-5, Mar. 2017.
D. Suzuki, M. Natsui, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, "Design of a Variation-Resilient Single-Ended Nonvolatile 6-Input Lookup Table Circuit with a Redundant-MTJ-Based Active Load for Smart IoT Applications," Institute of Engineering Technology (IET), Electronics Letters, vol. 53, No.7, pp. 456-458, Mar. 2017.

Peer-Reviewed International Conference Papers

N. Onizawa, S. Koshita, S. Sakamoto, M. Kawamata, and T. Hanyu, "Design of Stochastic Asymmetirc Compensation Filter for Auditory SignalProcessing," Proc. 5th IEEE Global Conference on Signal and Information Processing (GlobalSIP), pp. 1315-1319, Nov. 2017.
M. Natsui and T. Hanyu, "Energy-Efficient High-Performance Nonvolatile VLSI Processor with a Temporary-Data Reuse Technique," Extended Abstracts of 2017 International Conference on Solid State Devices and Materials (SSDM2017), pp.977-978, Sendai, Sept. 2017.
D. Suzuki and T. Hanyu, "Design of an MTJ-Oriented Nonvolatile Lookup Table Circuit with Write-Operation Minimizing," Extended Abstracts of the 2017 International Conference on Solid State Devices and Materials (SSDM2017), pp.195-196, Sendai, Sept. 2017.
M. Rizk, J.-P. Diguet, N. Onizawa, M. J. Sepulveda, Y. Akgul, V. Gripon, A. Baghdadi, and T. Hanyu, "NoC-MRAM Architecture for Memory-Based Computing: Database-Search Case Study," Proc. 15th IEEE International New Circuits and Systems Conference (NEWCAS), pp. 309-312, Jun. 2017.
N. Onizawa, S. Koshita, S. Sakamoto, M. Kawamata, and T. Hanyu, "Evaluation of Stochastic Cascaded IIR Filters," 47th IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 2017.
N. Onizawa, M. Imai, T. Hanyu and T. Yoneda, "MTJ-based asynchronous circuits for re-initialization free computing against power failures," Proc. of 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp.118-125, May 2017.

Invited Speeches/Invited Tutorials

T. Hanyu, "Challenge of MTJ-Based Nonvolatile Logic LSI for IoT Applications," Tohoku-Hanyang Workshop on Electronics and Communications Engineering (WECE), Aug. 2017.
T. Hanyu, "Challenge of Spintronics-Based Nonvolatile VLSI Processor with a Sudden Power-Outage Resilient In-Processor Checkpointing," 2017 Spintronics Workshop on LSI, P.3, Jun. 5, 2017.
T. Hanyu, "Challenge of MOS/MTJ-Hybrid Nonvolatile VLSI Processor for IoE Applications," Emerging Technologies of Communications, Microsystems, Optoelectronics and Sensors 2017 (ETCMOS 2017), Warsaw, Poland, May 30, 2017.
D. Suzuki and T. Hanyu, "MTJ-Based Nonvolatile FPGA; the Present and the Future Technology Trends," 26th International Workshop on Post-Binary ULSI Systems, p. 2, May, 2017.
T. Hanyu, "MTJ-Based Nonvolatile Logic-in-Memory Circuits with Self-Terminated Writing Mechanism for Ultra-Low-Power VLSI Processor," Special lecture at Nazarbayev Univ., Astana, Kazakhstan, May 4, 2017.
T. Hanyu, "Challenge of Spintronics-Device-Based Non-volatile Logic-in-Memory Architecture for Internet-of-Things Applications," BIT's 3rd Annual World Congress of Smart Materials-2017, P.262, Mar. 2017.
T. Hanyu, D. Suzuki, N. Onizawa, and M. Natsui, "Three-Terminal MTJ-Based Nonvolatile Logic Circuits with Self-Terminated Writing Mechanism for Ultra-Low-Power VLSI Processor," Design, Automation & Test in Europe (DATE), pp. 548-553, Mar. 2017.

[2016]

Journal Papers

K. Boga, F. Leduc-Primeaur, N. Onizawa, K. Matsumiya, T. Hanyu, and W. J. Gross, "A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception," Journal of Signal Processing Systems (JSPS), Dec. 2016.
T. Hanyu, T. Endoh, D. Suzuki, H. Koike, Y. Ma, N. Onizawa, M. Natsui, S. Ikeda, and H. Ohno, "Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing," Proc. IEEE, vol.104, no.10, pp.1844-1863, Oct. 2016.
N. Onizawa, D. Katagiri, W. J. Gross, and T. Hanyu, "Analog-to-Stochastic Converter Using Magnetic Tunnel Junction Devices for Vision Chips," IEEE Trans. on Nanotechnology, vol. 15, no. 5, pp. 705-714, Sep. 2016.
T. Endoh, H. Koike, S. Ikeda, T. Hanyu, and H. Ohno, "An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories -," IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), Vol. 6, No. 2, pp. 109-119, Jun. 2016.
N. Onizawa, H. Jarollahi, T. Hanyu, and W. J. Gross, "Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks," IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), Vol. 6, No.1, pp. 13-24, Mar. 2016.
Y. Ma, S. Miura, H. Honjo, S. Ikeda, T. Hanyu, H. Ohno, and T. Endoh,"A 600-µW Ultra-Low-Power Associative Processor for Image Pattern Recognition Employing MTJ-Based Nonvolatile Memories with Autonomic Intelligent Power-Gating (IPG) Scheme," Japanese Journal of Applied Physics (JJAP), Volume 55,Number 4S, pp. 04EF15-1-11, Mar. 2016.
N. Onizawa, N. Sakimura, R. Nebashi, T. Sugibayashi, and T. Hanyu, "Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory," Journal of Multiple Valued-Logic & Soft Computing (MVLSC), Vol. 26, Issue 1/2, pp. 125-140, 2016.

Peer-Reviewed International Conference Papers

D. Suzuki and T. Hanyu, "A Self-Terminated One-Phase Write Driver for Complementary-MTJ Based Memory Cells," Abst. 61st Annual Conference on Magnetism & Magnetic Materials (MMM), p. 554, Nov. 2016.
D. Suzuki and T. Hanyu, "A Self-Terminated Energy-Efficient Nonvolatile Flip-Flop Using 3-terminal Magnetic Tunnel Junction Device," Proc. of 2016 International Conference on Solid State Devices and Materials (SSDM2016), pp. 911-912, Sep. 2016.
N. Onizawa and T. Hanyu, "A Soft/Write-Error Resilient CMOS/MTJ Nonvolatile Flip-Flop Based on Majority-Decision Shared Writing," Proc. of 2016 International Conference on Solid State Devices and Materials (SSDM2016), pp. 79-80, Sep. 2016.
M. Natsui, A. Tamakoshi, T. Endoh, H. Ohno, and T. Hanyu, "Highly Reliable MTJ-Based Nonvolatile Logic-in-Memory LSI with Content-Aware Write Error Masking Scheme," Proc. of 2016 International Conference on Solid State Devices and Materials (SSDM2016), pp. 77-78, Sep. 2016.
A. Arash, F. Leduc-Primeau, N. Onizawa, T. Hanyu, and W. J. Gross, "VLSI Implementation of Deep Neural Networks Using Integral Stochastic Computing," Proc. 6th International Symposium on Turbo Codes & Iterative Information Processing, pp. 216-220, Sep. 2016.
D. Suzuki and T. Hanyu, "A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure," Proceeding of International Conference on Field-Programmable Logic and Applications (FPL), pp. 1-4, Aug. 2016.
M. Natsui, N. Sugaya, and T. Hanyu, "A Study of a Top-Down Error Correction Technique Using Recurrent-Neural-Network-Based Learning", Proc. 14th IEEE International New Circuits and Systems Conference (NEWCAS), Jun. 2016.
N. Onizawa, and T. Hanyu, "Redundant STT-MTJ-Based Nonvolatile Flip-Flops for Low Write-Error-Rate Operations," Proc. 14th IEEE International New Circuits and Systems Conference (NEWCAS), pp. 1-4, Jun. 2016.
M. Natsui, A. Tamakoshi, A. Mochizuki, H. Koike, H. Ohno, T. Endoh, and T. Hanyu, "Stochastic Behavior-Considered VLSI CAD Environment for MTJ/MOS-Hybrid Microprocessor Design," 2016 IEEE International Symposium on Circuits and Systems(ISCAS2016), pp. 1878-1881, May 2016.
S. Koshita, N. Onizawa, M. Abe, T. Hanyu, and M. Kawamata, "Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation," Proc. of the 46th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2016), pp. 223-228, May 2016.
N. Sugaya, M. Natsui, and T. Hanyu, "Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission," Proc. of the 46th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2016), pp. 72-77, May 2016.
D. Suzuki and T. Hanyu, "Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme," Proc. of the 46th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 5-10, May 2016.
N. Onizawa, S. Koshita, S. Sakamoto, M. Abe, M. Kawamata, and T. Hanyu, "Gammatone Filter Based on Stochastic Computation," Proc. 41st IEEE International Conference on Acoustic, Speech, and Signal Processing (ICASSP), pp. 1036-1040, Mar. 2016.

Invited Speeches/Invited Tutorials

M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, "Towards Ultra Low-Power and Highly Dependable VLSI Computing Based on MTJ-Based Nonvolatile Logic-in-Memory Architecture," Proc. of BIT�fs 6th Annual World Congress of Nano Science & Technology 2016 (Nano-S&T), Oct. 2016.
T. Hanyu, "Challenge of Spintronics-Based Nonvolatile Logic-in-Memory VLSI Architecture towards the IoE Era," 2016 Spintronics Workshop on LSI, P. 6, Jun. 2016.
T. Hanyu, "Challenge of MOS/MTJ-Hybrid Nonvolatile VLSI Processor for IoE Applications," VLSI Technology Short Course 2016, No.8, Jun. 2016.

Books

T. Hanyu, T. Endoh, S. Ikeda, T. Sugibayashi, N. Kasai, D. Suzuki, M. Natsui, H. Koike, and H. Ohno, "Beyond MRAM: Nonvolatile Logic-in-Memory VLSI, " Chapter 7 in Book: Introduction to Magnetic Random-Access Memory, edited by Bernard Dieny, Ronald B. Goldfarb, Kyung-Jin Lee, Dec. 2016, Wiley-IEEE Press ISBN: 978-1-119-00974-0

[2015]

Journal Papers

N. Onizawa, D. Katagiri, K. Matsumiya, W. J. Gross, and T. Hanyu, "Gabor Filter Based on Stochastic Computation," IEEE Signal Processing Letters, vol. 22, no. 9, pp. 1224-1228, Sep. 2015.
D. Suzuki and T. Hanyu, "Nonvolatile Field-Programmable Gate Array Using 2-Transistor-1-Magnetic-Tunnel-Junction-Vell-Based Multi-Context Array for Power and Area Efficient Dynamically Reconfigurable Logic," Japanse Journal of Applied Physics (JJAP), vol. 54, no. 4S, pp. 04DE01-1~04DE01-5, Mar. 2015.
H. Jarollahi, V. Gripon, N. Onizawa, and W. J. Gross, "Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks," IEEE Trans. VLSI Syst., vol. 23, no. 4, pp. 642-653, Apr. 2015.
H. Koike, T. Ohsawa, S. Miura, H. Honjo, S. Ikeda, T. Hanyu, H. Ohno, and T. Endoh, "Power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation," Japanese Journal of Applied Physics (JJAP) vol. 54, no. 4, pp. 04DE08, Apr. 2015
M. Natsui, D. Suzuki, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, T. Sugibayashi, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, "Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction," IEEE Journal of Solid-State Circuits (JSSC), vol. 50, no. 2, pp. 476-489, Feb. 2015.
D. Suzuki and T. Hanyu, "Magnetic-Tunnel-Junction Based Low-Energy Nonvolatile Flip-Flop Using An Area-Efficient Self-Terminated Write Driver," Journal of Applied Physics (JAP), vol. 117, pp. 17B504-1~17B504-3, Jan. 2015.

Peer-Reviewed International Conference Papers

A. Mochizuki, N. Onizawa, A. Tamakoshi, and T. Hanyu, "Multiple-Event-Transient Soft-Error Gate-Level Simulator for Harsh Radiation Environments," Proceedings of IEEE TENCON 2015, no.1658, Nov. 2015.
A. Mochizuki, N. Yube, and T. Hanyu, "Design of a Computational Nonvolatile RAM for a Greedy Energy-Efficient VLSI Processor," 41st Annual Conference of the IEEE Industrial Electronics Society (IECON2015), pp. 003283-003288, Nov. 2015.
K. Boga, N. Onizawa, F. L.-Primeau, K. Matsumiya, T. Hanyu, and W. Gross, "Stochastic Implementation of the Disparity Energy Model for Depth Perception," IEEE International Workshop on Signal Processing Systems (SiPS), Oct. 2015.
D. Suzuki and T. Hanyu, "Design of an MTJ-Based Nonvolatile Lookup Table Circuit Using an Energy-Efficient Single-Ended Logic-In-Memory Structure," Proc. IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 317-320, Aug. 2015.
N. Onizawa, S. Koshita, and T. Hanyu, "Scaled IIR Filter Based on Stochastic Computation," Proc. IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 297-300, Aug. 2015.
N. Onizawa, D. Katagiri, K. Matsumiya, W. J. Gross, and T. Hanyu, "Frequency-Flexible Stochastic Gabor Filter," Proc. 2015 IEEE International Conference on Digital Signal Processing (DSP), pp. 458-462, Jul. 2015.
N. Onizawa, A. Mochizuki, A. Tamakoshi, and T. Hanyu, "A Sudden Power-Outage Resilient Nonvolatile Microprocessor for Immediate System Recovery," IEEE/ACM Int. Symp. Nanoscale Architectures (NANOARCH), pp. 39-44, Jul. 2015.
D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, "Fabrication of a 3000-6-Input-LUTs Embedded and Block-Level Power-Gated Nonvolatile FPGA Chip Using p-MTJ-Based Logic-in-Memory Structure," Symp. VLSI Circuits Dig. Tech. Papers, pp. 172-173, Jun. 2015.
S. Oosawa, T. Konishi, N. Onizawa, and T. Hanyu, "Design of an STT-MTJ Based True Random Number Generator Using Digitally Controlled Probability-Locked Loop," Proc. 13th IEEE International NEWCAS Conference, pp. 468-471, pp. 1-4, Jun. 2015.
T. Hanyu, "Challenge of MOS/MTJ-Hybrid Integrated Circuits Based on Nonvolatile Logic-in-Memory Architecture," 2015 Spintronics Workshop on LSI, P.7, Jun. 15, 2015.
D. Katagiri, N. Onizawa, and T. Hanyu, "Early-Stage Operation-Skipping Scheme for Low-Power Stochastic Image Processors," Proc. IEEE International Symposium on Multiple-Valued Logic (ISMVL 2015), pp.109-114, May 2015.
T. Akutsu, M. Natsui, and T. Hanyu, "Write-Operation Frequency Reduction for Nonvolatile Logic LSI with a Short Break-Even Time," Proc. IEEE International Symposium on Multiple-Valued Logic (ISMVL 2015), pp.152-157, May 2015.
T. Hanyu, D. Suzuki, N. Onizawa, S. Matsunaga, M. Natsui, and A. Mochizuki "Spintronics-Based Nonvolatile Logic-in-Memory Architecture Towards an Ultra-Low-Power and Highly Reliable VLSI Computing Paradigm," , Proc. Design Automation & Test in Europe (DATE), pp. 1006-1011, Mar. 2015.
T. Yoneda, M. Imai, Hiroshi Saito, T. Hanyu, K. Kise, and Y. Nakamura, "An NoC-based evaluation platform for safety-critical automotive applications," Proc. 2015 Feb 5 IEEE Asia-Pacific Conferrence on Circuits and Systems (APCCAS), pp. 679-682, Feb. 2015.

Books

T. Hanyu, "Challenge of Nonvolatile Logic LSI Using MTJ-Based Logic-in-Memory Architecture," in Spintronics-based Computing, Zhao, Weisheng, Prenat, Guillaume, Eds., pp. 159-177 (Chapter 5), Spr. 2015.

[2014]

Journal Papers

H. Jarollahi, N. Onizawa, V. Gripon, N. Sakimura, T. Sugibayashi, T. Endoh, H. Ohno, and T. Hanyu, and W. J. Gross, "A Non-Volatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 4, no. 4, pp. 460-474, Dec. 2014.
D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu, "Cost-Efficient Self-Terminated Write Driver for Spin-Transfer-Torque RAM and Logic," IEEE Trans. Magn., vol. 50, no. 11, pp. 3402104~1-3402104~4, Nov. 2014.
N. Onizawa and T. Hanyu, "Soft-Error Tolerant Transistor/Magnetic-Tunnel-Junction Hybrid Non-Volatile C-element," IEICE Electronics Express (ELEX), vol. 11, no. 24, pp. 20141017, Nov. 2014.
N. Onizawa, W. J. Gross, T. Hanyu, and V. C. Gaudet, "Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes: Algorithm and Simulation Model," IEICE Trans. Inf. and Syst., vol. E97-D, no. 9, pp. 2286-2295, Sep. 2014.
A. Mochizuki, H. Shirahama, Y. Watanabe,and T. Hanyu, "Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip," IEICE Trans. Inf. and Syst., vol. E97-D, no. 9, pp. 2304-2311, Sep. 2014.
N. Onizawa, W. J. Gross, T. Hanyu, and V. C. Gaudet, "Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model," Journal of Signal Processing Systems (JSPS), vol. 76, no. 2, pp. 185-194, Aug. 2014.
D. Suzuki, N. Sakimura, M. Natsui, A. Mochizuki, T. Sugibayashi, T. Endoh, H. Ohno, and T. Hanyu, "A Compact Low-Power Nonvolatile Flip-Flop Using Domain-Wall-Motion-Device-Based Single-Ended Structure," IEICE Electronics Express (ELEX), vol. 11, no. 13, pp. 20140296~1-20140296~11, Jun. 2014.
N. Onizawa, A. Mochizuki, H. Shirahama, M. Imai, T. Yoneda, and T. Hanyu, "High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs" IEICE Trans. Inf. and Syst., vol. E97-D, no. 6, pp. 1546-1556, Jun. 2014.
T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, and T. Endoh, "Trend of tunnel magnetoresistance and variation in threshold voltage for keeping data load robustness of metal-oxide-semiconductor/magnetic tunnel junction hybrid latches," Journal of Applied Physics (JAP), vol. 115, pp. 17C728, May 2014.
N. Sakimura, R. Nebashi, M. Natsui, H. Ohno, T. Sugibayashi, and T. Hanyu, "Analysis of single-event upset of magnetic tunnel junction used in spintronic circuits caused by radiation-induced current," Journal of Applied Physics (JAP), vol. 115, pp. 17B748, May 2014.
S. Matsunaga, A. Mochizuki, N. Sakimura, R. Nebashi, T. Sugibayashi, T. Endoh, H. Ohno, and T. Hanyu, "Complementary 5T-4MTJ Nonvolatile TCAM Cell Circuit with Phase-Selective Parallel Writing Scheme," IEICE Electronics Express (ELEX), vol. 11, no. 10, pp. 20140297~1-20140297~7, Apr. 2014.
H. Jarollahi, N. Onizawa, V. Gripon, and W. J. Gross, "Algorithm and Architecture of Fully-Parallel Associative Memories Based on Sparse Clustered Networks," Journal of Signal Processing Systems (JSPS), vo. 76, no. 3, pp. 235-247, Apr. 2014.
N. Onizawa, S. Matsunaga, V. C. Gaudet, W. J. Gross, and T. Hanyu, "High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism," IEEE Trans. Circuits and Syst. I Reg. Papers, vol. 61, no. 3, pp. 865-876, Mar. 2014.
N. Onizawa, A. Matsumoto, T. Funazaki, and T. Hanyu, "High-Throughput Compact Delay-Insensitive Asynchronous NoC Router," IEEE Trans. Computers, vol. 63, no. 3, pp. 637-649, Mar. 2014.
D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, K. Kinoshita, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, "Design and Fabrication of a Perpendicular Magnetic Tunnel Junction Based Nonvolatile Programmable Switch Achieving 40% Less Area Using Shared-Control Transistor Structure," Journal of Applied Physics (JAP), vol. 115, no. 17, pp. 17B742-1~17B742-3, Mar. 2014.
H. Koike, T. Ohsawa, S. Miura, H. Honjo, S. Ikeda, T. Hanyu, H. Ohno, and T. Endoh, "Wide operational margin capability of 1 kbit spin-transfer-torque memory array chip with 1-PMOS and 1-bottom-pin-magnetic-tunnel-junction type cell," Japanese Journal of Applied Physics, vol. 53, no. 4S, pp. 04ED13, Mar. 2014.
T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, and T. Endoh, "A two-transistor bootstrap type selective device for spin-transfer-torque magnetic tunnel junctions," Japanese Journal of Applied Physics (JJAP), vol. 53, no. 4, pp. 04ED03, Feb. 2014.
D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu, "Design and Evaluation of a 67% Area-Less 64-Bit Parallel Reconfigurable 6-Input Nonvolatile Logic Element Using Domain-Wall Motion Devices," Japanese Journal of Applied Physics (JJAP), vol. 53, no. 4S, pp. 04EM03-1~04EM03-5, Feb. 2014.
S. Matsunaga, A. Mochizuki, T. Endoh, H. Ohno, and T. Hanyu, "Design of an Energy-Efficient 2T-2MTJ Nonvolatile TCAM Based on a Parallel-Serial-Combined Search Scheme," IEICE Electronics Express (ELEX), vol. 11, no. 3, pp. 20131006-1~20131006-10, Jan. 2014.

Peer-Reviewed International Conference Papers

T. Hanyu, D. Suzuki, A. Mochizuki, M. Natsui, N. Onizawa, T. Sugibayashi, S. Ikeda, T. Endoh, and H. Ohno, "Challenge of MOS/MTJ-Hybrid Nonvolatile Logic-in-Memory Architecture in Dark-Silicon Era," IEEE International Electron Devices Meeting (IEDM) Technical Digest, pp 28.2.1-28.2.3, Dec. 2014.
D. Suzuki and T. Hanyu, "MTJ-Based Low-Energy Nonvolatile Flip-Flop Using Area-Efficient Self-Terminated Write Driver," Abst. 59th Annual Conference on Magnetism & Magnetic Materials (MMM), p. 813, Nov. 2014.
A. Mochizuki, H. Shirahama, N. Onizawa, and T. Hanyu, "Highly Reliable Single-Ended Current-Mode Circuit for an Inter-Chip Asynchronous Communication Link," Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 683-686, Nov. 2014.
H. Jarollahi, N. Onizawa, T. Hanyu, and W. J. Gross, "Algorithm and Architecture for a Multiple-Field Context-Driven Search Engine Using Fully-Parallel Clustered Associative Memories," Proc. 2014 IEEE International Workshop on Signal Processing Systems (SIPS), pp.133-138, Oct. 2014.
D. Suzuki and T. Hanyu, "Nonvolatile FPGA Using 2T-1MTJ-Cell-Based Multi-Context Array for Power and Area Efficient Dynamically Reconfigurable Logic," Ext. Abst. International Conference on Solid State Devices and Materials (SSDM), pp. 450-451, Sep. 2014.
N. Onizawa, D. Katagiri, W. J. Gross, and T. Hanyu, "Analog-to-Stochastic Converter Using Magnetic-Tunnel Junction Devices," Proc. IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pp.59-64, Jul. 2014.
H. Shirahama, A. Mochizuki, Y. Watanabe, and T. Hanyu, "Energy-Aware Current-Mode Inter-Chip Link for a Dependable GALS NoC Platform," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1865-1868, Jun. 2014.
R. Nebashi, N. Sakimura, H. Honjo, A. Morioka, Y. Tsuji, K. Ishihara, K. Tokutome, S. Miura, S. Fukami, K. Kinoshita, T. Hanyu, T. Endoh, N. Kasai, H. Ohno, and T. Sugibayashi, "A Delay Circuit with 4-Terminal Magnetic-Random-Access-Memory Device for Power-Efficient Time-Domain Signal Processing," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1588-1591, Jun. 2014.
M. Natsui and T. Hanyu, "Fabrication of a MTJ-Based Multilevel Resistor Towards Process-Variation-Resilient Logic LSI," Proc. 12th IEEE International NEWCAS Conference, pp. 468-471, Jun. 2014.
N. Onizawa, S. Matsunaga, and T. Hanyu, "Design of a Soft-Error Tolerant 9-Transistor/6-Magnetic-Tunnel-Junction Hybrid Cell Based Nonvolatile TCAM," Proc. 12th IEEE International NEWCAS Conference, pp. 193-196, Jun. 2014.
N. Onizawa, S. Matsunaga, and T. Hanyu, "A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure," 20th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 1-8, May 2014 (Best Paper Finalist).
D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu, "Optimally Self-Terminated Compact Switching Circuit Using Continuous Voltage Monitoring Achieving High Read Margin for STT MRAM and Logic," Abst. International Magnetics Conference (INTERMAG), pp. 2506-2507, May 2014.
M. Natsui and T. Hanyu, "Variation-Effect Analysis of MTJ-Based Multiple-Valued Programmable Resistors," Proc. 44th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 243-247, May 2014.
H. Jarollahi, N. Onizawa, T. Hanyu, and W. J. Gross, "Associative Memories Based on Multiple-Valued Sparse Clustered Networks," Proc. 44th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 208-213, May 2014.
N. Onizawa, S. Matsunaga, N. Sakimura, R. Nebashi, T. Sugibayashi, and T. Hanyu, "Soft-Delay-Error Evaluation in Content-Addressable Memory," Proc. 44th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 220-225, May 2014.
A. Mochizuki, H. Shirahama, and T. Hanyu, "Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-Chip Asynchronous Communication Link," Proc. 44th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 67-72, May 2014.
T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, and T. Endoh, "Studies on read-stability and write-ability of fast access STT-MRAMs," 2014 Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), pp. 6839665, Apr. 2014.
N. Sakimura, Y. Tsuji, R. Nebashi, H. Honjo, A. Morioka, K. Ishihara, K. Kinoshita, S. Fukami, S. Miura, N. Kasai, T. Endoh, H. Ohno, T. Hanyu, and T. Sugibayashi, "A 90nm 20MHz Fully Nonvolatile Microcontroller for Standby-Power-Critical Applications," IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp.184-185, Feb. 2014.

Invited Speeches/Invited Tutorials

A. Mochizuki, M. Natsui, N. Sakimura, T. Sugibayashi, and T. Hanyu, "Challenge of Nonvolatile TCAM Design Automation," Booklet of the 23rd International Workshop on Post-Binary ULSI Systems, p. 1, May 2014.

[2013]

Journal Papers

M. Natsui and T. Hanyu, "Design of Process-Variation-Resilient Analog Basic Components Using Magnetic-Tunnel-Junction Devices," Journal of Multiple-Valued Logic and Soft Computing, vol.21, no.5-6, pp.597-608, Dec. 2013.
T. Hanyu, "Challenge of MTJ-Based Nonvolatile Logic-in-Memory Architecture for Dark-Silicon Logic LSI," SPIN, vol. 3, no. 4, pp. 1340014-1~1340014-8, Dec. 2013.
D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, K. Kinoshita, H. Sato, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, "Fabrication of a Magnetic Tunnel Junction-Based 240-Tile Nonvolatile Field-Programmable Gate Array Chip Skipping Wasted Write Operations for Greedy Power-Reduced Logic Applications," IEICE Electronics Express (ELEX), vol. 10, no. 23, pp. 20130772-1~20130772-10, Nov. 2013.
N. Onizawa, A. Matsumoto, and T. Hanyu, "Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links," IEICE Trans. Inf. & Syst., vol. E96D, no. 9, pp. 1952-1961, Sep. 2013.
T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Hanyu, H. Ohno and T. Endoh, "A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme," IEEE Journal of Solid-State Circuits (JSSC), vol. 48, no. 6, pp. 1511~1520, Jun. 2013.
A. Matsumoto, T. Kawano, N. Onizawa, and T. Hanyu, "Control-Information Sharing Asynchronous Fine-Grained Power-Gating Techniques and Its Application to On-Chip Routers," IEICE Trans. on Electron. (Japanese), vol. J96-C, no. 5, pp. 73-84, May 2013.
N. Onizawa, S. Matsunaga, V. C. Gaudet, W. J. Gross, and T. Hanyu, "High-Throughput CAM Based on a Synchronous Overlapped Search Scheme," IEICE Electronics Express (ELEX), vol. 10, no. 7, pp. 20130148-1~20130148-9, Apr. 2013.
D. Suzuki, Y. Lin, M. Natsui, and T. Hanyu, "A 71%-Area-Reduced Six-Input Nonvolatile Lookup-Table Circuit Using a Three-Terminal Magnetic-Tunnel-Junction-Based Single-Ended Structure," Japanese Journal of Applied Physics (JJAP) vol. 52, no. 4, pp. 04CM04-1~04CM04-6, Mar. 2013.

Peer-Reviewed International Conference Papers

D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, K. Kinoshita, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu, "Fabrication of a Perpendicular-MTJ-Based Compact Nonvolatile Programmable Switch Using Shared-Write-Control-Transistor Structure," Abst. 58th Annual Conference on Magnetism & Magnetic Materials (MMM), p. 233, Nov. 2013.
N. Onizawa, S. Matsunaga, V. C. Gaudet, W. J. Gross, and T. Hanyu, "Probabilistic Search Schemes for High-Speed Low-Power Content-Addressable Memories," Proc. International Conference on Analog VLSI Circuits, pp. 100-105, Oct. 2013.
D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu, "Design of a Three-Terminal MTJ-Based Nonvolatile Logic Element with a 2-ns 64-Bit-Parallel Reconfiguration Capability," Ext. Abst. International Conference on Solid State Devices and Materials (SSDM), pp. 386-387, Sep. 2013.
S. Matsunaga, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, T. Sugibayashi, S. Miura, H. Honjo, K. Kinoshita, H. Sato, S. Fukami, M. Natsui, A. Mochizuki, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, "Fabrication of a 99%-Energy-Less Nonvolatile Multi-Functional CAM Chip Using Hierarchical Power Gating for a Massively-Parallel Full-Text-Search Engine," Symposium on VLSI Circuits Digest of Technical Papers, pp. 106-107, Jun. 2013.
M. Natsui, N. Sakimura, T. Sugibayashi, and T. Hanyu, "MTJ/MOS-Hybrid Logic-Circuit Design Flow for Nonvolatile Logic-in-Memory LSI," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 105-108, May 2013.
N. Onizawa, W. J. Gross, and T. Hanyu, "A Low-Energy Variation-Tolerant TCAM for Network Intrusion Detection Systems," Proc. 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 8-15, May 2013.
M. Natsui, K. Kashiuchi, and T. Hanyu, "Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications," Proc. 43rd IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 147-151, May 2013.
N. Onizawa, W. J. Gross, T. Hanyu, and V. C. Gaudet, "Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating," 43rd IEEE International Symposium on Multiple-Valued Logic (ISMVL), Proc. pp. 254-259, May 2013.
T. Hanyu, Y. Watanabe, and A. Matsumoto, "Accurate and High-Speed Asynchronous Network-on-Chip Simulation Using Physical Wire-Delay Information," Proc. 43rd IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 266-271, May 2013.
M. Natsui, D. Suzuki, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, T. Sugibayashi, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, "Nonvolatile Logic-in-Memory Array Processor in 90nm MTJ/MOS Achieving 75% Leakage Reduction Using Cycle-Based Power Gating," IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pp. 194-195, Feb. 2013.

Invited Speeches/Invited Tutorials

T. Hanyu, "Towards a Nonvolatile VLSI Processor Using MTJ/MOS-Hybrid Logic-in-Memory Architecture," Non-Volatile Memory Technology Symposium (NVMTS), D-2, Aug. 2013. (Invited Talk).
T. Hanyu, "Challenge of MTJ/MOS-Hybrid Logic-in-Memory Architecture for Nonvolatile VLSI Processor," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 117-120, May 2013 (Invited Talk).

[2012]

Journal Papers

M. Natsui, T. Arimitsu, and T. Hanyu, "Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique," Journal of Multiple-Valued Logic and Soft Computing, vol. 19, no. 1-3, pp. 219-231, Sep. 2012.
N. Onizawa, A. Matsumoto, and T. Hanyu, "Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling," IEICE Transactions on Fundamentals, vol. E95-A, no. 6, pp. 1018-1029, Jun. 2012.
D. Suzuki, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, "Design of a Compact Nonvolatile Four-Input Logic Element Using a Magnetic-Tunnel-Junction and Metal-Oxide-Semiconductor Hybrid Structure," Japanese Journal of Applied Physics (JJAP) vol. 51, no. 4, pp. 04DM02~1-04DM02~5, Apr. 2012
S. Matsunaga, A. Katsumata, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, "Design of a 270ps-Access 7T-2MTJ-Cell Nonvolatile Ternary Content-Addressable Memory," Journal of Applied Physics (JAP), vol. 111, issue 7, pp. 07E336~1-07E336~3, Mar. 2012.
S. Matsunaga, A. Katsumata, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, "Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory," Japanese Journal of Applied Physics (JJAP), vol. 51, no. 2, pp. 02BM06~11-02BM06~6, Feb. 2012.
D. Suzuki, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, "Six-input Lookup Table Circuit with 62% Fewer Transistors Using Nonvolatile Logic-in-Memory Architecture with Series/Parallel-Connected Magnetic Tunnel Junctions," Journal of Applied Physics (JAP), vol. 111, issue 7, pp. 07E318~1-07E318~3, Feb. 2012.

Peer-Reviewed International Conference Papers

T. Yoneda, M. Imai, N. Onizawa, A. Matsumoto, and T. Hanyu, "Multi-Chip NoCs for Automotive Applications," Proc. 18th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), pp. 105-110, Nov. 2012.
N. Onizawa, W. J. Gross, T. Hanyu, and V. C. Gaudet, "Clockless Stochastic Decoding of Low-Density Parity-Check Codes," Proc. Workshop on Signal Processing Systems (SiPS), pp. 143-148, Oct. 2012.
D. Suzuki, Y. Lin, M. Natsui, and T. Hanyu, "Design of Compact Nonvolatile Lookup-Table Circuit Using Three-Terminal Magnetic-Tunnel-Junction-Based Single-Ended Structure," Ext. Abst. International Conference on Solid State Devices and Materials (SSDM), pp. 392-393, Sep. 2012.
D. Suzuki, M. Natsui, and T. Hanyu, "Area-Efficient LUT Circuit Design Based on Asymmetry of MTJ's Current Switching for a Nonvolatile FPGA," Proc. 55th IEEE Midwest Symposium on Circuits and Systems (MWSCAS), pp. 334-337, Aug. 2012.
L. Montesi, Z. Zilic, T. Hanyu, and D. Suzuki, "Building Blocks to Use in Innovative Non-Volatile FPGA Architecture Based on MTJs," Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 302-307, Aug. 2012.
T. Hanyu, "Challenge of Nonvolatile Logic-in-Memory Architecture Towards Cool LSI Chips," 2012 Spintronics Workshop on LSI, p. 8, Jun. 2012.
S. Matsunaga, S. Miura, H. Honjou, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, "A 3.14 μm² 4T-2MTJ-Cell Fully Parallel TCAM Based on Nonvolatile Logic-in-Memory Architecture," Symposium on VLSI Circuits Digest of Technical Papers, pp. 44-45, Jun. 2012.
T. Ohsawa, H. Koike, S. Miura, H. Honjou, K. Tokutome, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, "1Mb 4T-2MTJ Nonvolatile STT-RAM for Embedded Memories Using 32b Fine-Grained Power Gating Technique with 1.0ns/200ps Wake-up/Power-off Times," Symposium on VLSI Circuits Digest of Technical Papers, pp. 46-47, Jun. 2012.
Y. Tsuji, R. Nebashi, N. Sakimura, A. Morioka, H. Honjo, K. Tokutome, S. Miura, T. Suzuki, S. Fukami, K. Kinoshita, T. Hanyu, T. Endoh, N. Kasai, H. Ohno, and T. Sugibayashi, "Spintronics Primitive Gate with High Error Correction Efficiency 6(P_error)² for Logic-in Memory Architecture," Symposium on VLSI Technology Digest of Technical Papers, pp. 63-64, Jun. 2012.
T. Endoh, T. Ohsawa, H. Koike, T. Hanyu, and H. Ohno, "Restructuring of Memory Hierarchy in Computing System with Spintronics-Based Technologies," Symposium on VLSI Circuits Digest of Technical Papers, pp. 89-90, Jun. 2012.
M. Natsui and T. Hanyu, "Scalable Serial-Configuration Scheme for MTJ/MOS-Hybrid Variation-Resilient VLSI System," Proc. 10th IEEE International NEWCAS Conference, pp. 97-100, Jun. 2012.
M. Sihotang, S. Matsunaga, and T. Hanyu, "Fine-Grained Power-Gating Scheme of a Nonvolatile Logic-in-Memory Circuit for Low-Power Motion-Vector Extraction," Proc. 10th IEEE International NEWCAS Conference, pp. 485-488, Jun. 2012.
N. Sakimura, R. Nebashi, Y. Tsuji, H. Honjo, T. Sugibayashi, H. Koike, T. Ohsawa, S. Fukami, T. Hanyu, H. Ohno and T. Endoh, "High-speed simulator including accurate MTJ models for spintronics integrated circuit design," 2012 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1971~1974, May 2012.
N. Onizawa, S. Matsunaga, V. C. Gaudet, and T. Hanyu, "High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism," Proc. International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 41-48, May 2012.
A. Matsumoto, N. Onizawa, and T. Hanyu, "Systematic Coding Schemes for Low-Power Multiple-Valued Current-Mode Asynchronous Communication Links," Proc. 42nd IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 13-18, May 2012.
M. Natsui, T. Nagashima, and T. Hanyu, "Process-Variation-Resilient OTA Using MTJ-Based Multi-Level Resistance Control," Proc. 42nd IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 214-219, May 2012.
S. Matsunaga and T. Hanyu, "Quaternary 1T-2MTJ Cell Circuit for a High-Density and a High-Throughput Nonvolatile Bit-Serial CAM," Proc. 42nd IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 98-103, May 2012.
N. Onizawa, V. C. Gaudet, T. Hanyu, and W. J. Gross, "Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes," 42nd IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 92-97, May 2012.
Y. K. Kim, M. Natsui, and T. Hanyu, "Variation-Resilient Current-Mode Logic Circuit Design Using MTJ Devices," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2705-2708, May 2012.
S. Matsunaga, M. Natsui, S. Ikeda, K. Miura, T. Endoh, H. Ohno, and T. Hanyu, "Implementation of a Perpendicular MTJ-Based Read-Disturb-Tolerant 2T-2R Nonvolatile TCAM Based on a Reversed Current Reading Scheme," Proc. Asia and South Pacific Design Automation Confrence (ASP-DAC), pp. 475-476, Jan. 2012.

Invited Speeches/Invited Tutorials

T. Hanyu, "Nonvolatile Logic-in-Memory Architecture Using an MTJ/MOS-Hybrid Structure and Its Applications," Proc. IEEE COOL Chips XV, pp. 1-2, Apr. 2012 (Invited Talk).

[2011]

Journal Papers

N. Onizawa, V. C. Gaudet, and T. Hanyu, "Low-Energy Asynchronous Interleaver for Clockless Fully-Parallel LDPC Decoding," IEEE Trans. Circuits and Syst., Part I, vol. 58, no. 8, pp. 1933-1943, Aug. 2011.
S. Hanzawa and T. Hanyu, "Design of an 8-nsec 72-bit-Parallel-Search Content-Addressable Memory Using a Phase-Change Device," IEICE Trans. Electron., vol. E94-C, no. 8, pp. 1302-1310, Aug. 2011.
S. Matsunaga, M. Natsui, S. Ikeda, K. Miura, T. Endoh, H. Ohno, and T. Hanyu, "Design and Fabrication of a One-Transistor/One-Resistor Nonvolatile Binary Content-Addressable Memory Using Perpendicular Magnetic Tunnel Junction Devices with a Fine-Grained Power-Gating Scheme," Japanese Journal of Applied Physics (JJAP), vol. 50, no. 6R, pp. 063004~1-063004~7, Jun. 2011.

Internationl Conference Papers

M. Natsui, Y. K. Kim, and T. Hanyu,"MTJ-Based Optimal Vth-Tuning Technique for a Process-Variation-Aware VLSI processor," Abst. 56th Annual Conference on Magnetism & Magnetic Materials (MMM), pp. 480-481, Nov. 2011.
S. Matsunaga, A. Katsumata, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, "Design of a 270ps-Access 7T-2MTJ-Cell Nonvolatile Ternary Content-Addressable Memory," Abst. 56th Annual Conference on Magnetism & Magnetic Materials (MMM), p. 479, Nov. 2011.
D. Suzuki, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, "50%-Transistor-Less Standby-Power-Free 6-input LUT Circuit Using Redundant MTJ-Based Nonvolatile Logic-in-Memory Architecture," Abst. 56th Annual Conference on Magnetism & Magnetic Materials (MMM), p. 480, Nov. 2011.
D. Suzuki, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, "A Compact Nonvolatile Logic Element Using an MTJ/MOS-Hybrid Structure," Ext. Abst. International Conference on Solid State Devices and Materials (SSDM), pp. 1464-1465, Sep. 2011.
S. Matsunaga, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, "High-Speed-Search Nonvolatile TCAM Using MTJ Devices," Ext. Abst. International Conference on Solid State Devices and Materials (SSDM), pp. 454-455, Sep. 2011.
S. Matsunaga, A. Katsumata, M. Natsui, S. Fukami, T. Endoh, H. Ohno, and T. Hanyu, "Fully Parallel 6T-2MTJ Nonvolatile TCAM with Single-Transistor-Based Self Match-Line Discharge Control," Symposium on VLSI Circuits Digest of Technical Papers, pp. 298-299, Jun. 2011.
T. Kawano, N. Onizawa, A. Matsumoto, and T. Hanyu, "Adjacent-State Monitoring Based Fine-Grained Power-Gating Scheme for a Low-Power Asynchronous Pipelined System," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2067-2070, May 2011.
S. Matsunaga, A. Katsumata, M. Natsui, and T. Hanyu, "Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme," 41st IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 99-104, May 2011.
A. Matsumoto, N. Onizawa and T. Hanyu, "Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links," Proc. 41th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 236-241, May 2011.
N. Onizawa, A. Matsumoto, and T. Hanyu, "Interconnect-Fault-Resilient Delay-Insensitive Asynchronous Communication Link Based on Current-Flow Monitoring," Proc. Design Automation & Test in Europe (DATE), pp. 776-781, Mar. 2011.

Invited Speeches/Invited Tutorials

T. Hanyu, "MTJ-based Nonvolatile Logic-in-Memory Architecture and Its Application," 11th Non-Volatile Memory Technology Symposium (NVMTS), Nov. 2011 (Invited Talk).

Books

N. Onizawa, T. Funazaki, A. Matsumoto, and T. Hanyu, "Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model,�h Chapter in Book: Designing Very Large Scale Integration Systems: Emerging Trends & Challenges, Springer, pp. 17-30, 2011.

[2010]

Journal Papers

H. Shirahama, T. Matsuura, M. Natsui, and T. Hanyu, "Energy-Aware Multiple-Valued Current-Mode Sequential Circuit Using a Completion-Detection Scheme," IEICE Trans. Inf. & Syst., vol. E93-D, no. 8, pp. 2080-2088, Aug. 2010.
N. Onizawa and T. Hanyu, "Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link," IEICE Trans. Inf. & Syst., vol. E93-D, no. 8, pp. 2089-2099, Aug. 2010.
S. Matsunaga, M. Natsui, K. Hiyama, T. Endoh, H. Ohno, and T. Hanyu, "Fine-Grained Power-Gating Scheme of a Metal-Oxide-Semiconductor and Magnetic-Tunnel-Junction-Hybrid Bit-Serial Ternary Content-Addressable Memory," Japanese Journal of Applied Physics (JJAP), vol. 49, no. 4S, pp. 04DM05~1-04DM05~5, Apr. 2010.
N. Onizawa, T. Hanyu, and V. C. Gaudet, "Design of High-Throughput Fully-Parallel LDPC Decoders Based on Wire Partitioning," IEEE Trans. VLSI Syst., vol. 18, no. 3, pp. 482-489, Mar. 2010.
A. Hirosaki, A. Matsumoto, and T. Hanyu, "Design of a Threshold-Variation-Aware Multiple-Valued Current-Mode Circuit Using TMR Devices," IEICE Trans.Inf. & Syst. (Japanese Edition), vol.J93-D, no. 1, pp. 10-19, Jan. 2010.

Internationl Conference Papers

Y. Lin, D. Suzuki, M. Natsui, and T. Hanyu, "MTJ-Based Nonvolatile Reconfigurable LSI with Fine Grained Power Management," Proc. Japan-China-Korea Conference on Electronics & Communications (GWEI), p.JCK-P-17, Nov. 2010.
Y. K. Kim, M. Natsui, and T. Hanyu, "Design of a Dependable Logic Circuit Using Nonvolatile Programmable Devices," Proc. Japan-China-Korea Conference on Electronics & Communications (GWEI), p. JCK-P-18, Nov. 2010.
D. Suzuki, M. Natsui, H. Ohno, and T. Hanyu, "Design of a Process-Variation-Aware Nonvolatile MTJ-Based Lookup-Table Circuit," Ext. Abst. International Conference on Solid State Devices and Materials (SSDM), pp. 1146-1147, Sep. 2010.
S. Matsunaga, M. Natsui, H. Ohno, and T. Hanyu, "Power-Aware Bit-Serial Binary Content-Addressable Memory Using Magnetic-Tunnel-Junction-Based Fine-Grained Power-Gating Scheme," Ext. Abst. International Conference on Solid State Devices and Materials (SSDM), pp. 565-566, Sep. 2010.
T. Hanyu, "Logic-in-Memory Architecture Using Si-MOSFETs and Magnetic Tunnel Junctions," Proc. 6th International Conference on Physics and Applications of Spin Related Phenomena in Semiconductors (PASPS-VI), p. 176, Aug. 2010.
N. Onizawa, T. Funazaki, A. Matsumoto, and T. Hanyu, "Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model," Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 357-362, Jul. 2010.
M. Natsui and T. Hanyu, "Process-Variation-Aware VLSI Design Using Emerging Functional Devices and Its Impact," Booklet of the 19th International Workshop on Post-Binary ULSI Systems, pp. 20-25, May 2010.
A. Matsumoto, N. Onizawa, and T. Hanyu, "One-Color Two-Phase Asynchronous Communication Links Based on Multiple-Valued Simultaneous Control," Proc. 40th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 211-216, May 2010.
M. Natsui, T. Arimitsu, and T. Hanyu, "Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control," Proc. 40th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 235-240, May 2010.
N. Onizawa and T. Hanyu, "High-Throughput Protocol Converter Based on Independent Encoding/Decoding Scheme for Asynchronous Network-on-Chip," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 157-160, May 2010.

Invited Speeches/Invited Tutorials

T. Hanyu, "Nonvolatile FPGAs Using Nonvolatile Logic-in-Memory Architecture," ITRS Workshop on Emerging Spin and Carbon Based Emerging Logic Devices, ESSDERC, Sep. 2010 (Invited).
T. Hanyu (Panelist), Rump Session: The Future of Embedded Memory, 2010 Symposia on VLSI Technology and Circuits, Jun. 2010 (Invited).
T. Hanyu, "MOS/MTJ-Hybrid Circuit with Nonvolatile Logic-in-Memory Architecture and Its Impact," Proc. 28th IEEE VLSI Test Symposium, p. 258, Apr. 2010 (Invited).

[2009]

Journal Papers

D. Suzuki, M. Natsui, and T. Hanyu, "Design of a Lookup Table Circuit Based on TMR Logic and Its Application to an Immediate Wake-Upable FPGA," IEICE Trans. Electron. (Japanese), vol. J92-C, no. 7, pp. 233-240, July 2009.
N. Onizawa, T. Hanyu, and V. C. Gaudet, "High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving," IEICE Trans. Electron., vol. E92-C, no. 6, pp. 867-874, Jun. 2009.
S. Matsunaga, K. Hiyama, A. Matsumoto, S. Ikeda, H. Hasegawa, K. Miura, J. Hayakawa, T. Endoh, H. Ohno, and T. Hanyu, "Standby-Power-Free Compact Ternary Content-Addressable Memory Cell Chip Using Magnetic Tunnel Junction Devices," Applied Physics Express (APEX), vol. 2, no. 2, pp. 023004~1-023004~3, Feb. 2009.

Internationl Conference Papers

S. Matsunaga, A. Matsumoto, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, "Fine-Grain Power-Gating Scheme of a CMOS/MTJ-Hybrid Bit-Serial Ternary Content-Addressable Memory," Ext. Abst. International Conference on Solid State Devices and Materials (SSDM), pp. 1382-1383, Oct. 2009.
D. Suzuki, M. Natsui, S. Ikeda, H. Hasegawa, K. Miura, J. Hayakawa, T. Endoh, H. Ohno, and T. Hanyu, "Fabrication of a Nonvolatile Lookup-Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array," Symposium on VLSI Circuits Digest of Technical Papers, pp. 80-81, Jun. 2009.
N. Onizawa and T. Hanyu, "Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control," Proc. 39th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 36-41, May 2009.
T. Matsuura, H. Shirahama, M. Natsui, and T. Hanyu, "Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System," Proc. 39th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 60-65, May 2009.
Y. Ohtake, N. Onizawa, and T. Hanyu, "High-Performance Asynchronous Intra-Chip Communication Link Based on a Multiple-Valued Current-Mode Single-Track Scheme," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1000-1003, May 2009.

Invited Speeches/Invited Tutorials

M. Natsui and T. Hanyu, "MOS/MTJ-Hybrid Circuit with Nonvolatile Logic-in-Memory Architecture," Ext. Abst. International Conference on Solid State Devices and Materials(SSDM), pp. 1398-1399, Oct. 2009 (Invited).
T. Hanyu, "Ultra-Low Power IC Technology Integrated with Innovative Materials," 2009 International Conference on Solid-State Devices and Materials, Workshop, pp. 1-9, Oct. 2009.�iInvited Talk�j
T. Hanyu, "A MOS/MTJ-Hybrid Circuit with Nonvolatile Logic-in-Memory Architecture," Advances in Magnetic Nanostructures, Engineering Conferences International (ECI), p. 21, Oct. 2009.�iInvited Talk�j
S. Matsunaga, J. Hayakawa, S. Ikeda, K. Miura, T. Endoh, H. Ohno, and T. Hanyu, "MTJ-Based Nonvolatile Logic-in-Memory Circuit, Future Prospects and Issues," Design Automation and Test in Europe (DATE), pp. 433-436, Apr. 2009 (Invited).

[2008]

Journal Papers

S. Matsunaga, J. Hayakawa, S. Ikeda, K. Miura, H. Hasegawa, T. Endoh, H. Ohno, and T. Hanyu, "Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions," Applied Physics Express (APEX), vol. 1, no. 9, pp. 091301~1-091301~3, Aug. 2008.
M. Miura and T. Hanyu, "Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation," IEICE Trans. Electron., vol. E91-C, no. 4, pp.589-594, Apr. 2008.
K. Mizusawa, N. Onizawa, and T. Hanyu, "Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling," IEICE Trans. Electron., vol. E91-C, no. 4, pp.581-588, Apr. 2008.

Internationl Conference Papers

S. Matsunaga, J. Hayakawa, S. Ikeda, K. Miura, T. Endoh, H. Ohno, and T. Hanyu, "Fabrication of a Standby-Power-Free TMR-Based Nonvolatile Memory-in-Logic Circuit Chip with a Spin-Injection Write Scheme," Ext. Abst. International Conference on Solid State Devices and Materials (SSDM), pp. 274-275, Sep. 2008.
D. Suzuki, T. Endoh, and T. Hanyu, "TMR-Logic-Based LUT for Quickly Wake-Up FPGA," Proc. 51st IEEE Midwest Symposium on Circuits and Systems (MWSCAS), pp. 326-329, Aug. 2008.
H. Shirahama and T. Hanyu, "Design of High-Performance Quaternary Adders Based on Output-Generator Sharing," Proc. 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 8-13, May 2008.
A. Hirosaki, M. Miura, A. Matsumoto, and T. Hanyu, "Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices," Proc. 38th IEEE International Symposium on Multiple-Valued Logic, pp. 14-19, May 2008.
T. Nagai, N. Onizawa, and T. Hanyu, "High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit," Proc. 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 70-75, May 2008.
A. Matsumoto, T. Yoneda, and T. Hanyu, "High-level Synthesis of Asynchronous Circuits and Its Optimization," Booklet of the 17th International Workshop on Post-Binary ULSI Systems, May 2008.

Invited Speeches/Invited Tutorials

T. Hanyu, "TMR Logic: Nonvolatile Logic Circuit Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions," Pacific Rim Meeting on Electrochemical and Solid-State Science (PRiME), 2105, Oct. 2008 (Invited).

[2007]

Journal Papers

S. Ikeda, J. Hayakawa, Y. M. Lee, F. Matsukura, Y. Ohno, T. Hanyu, and H. Ohno, "Magnetic Tunnel Junctions for Spintronic Memories and Beyond," IEEE Trans. Electron Devices, vol.54, no.05, pp.991-1002, May 2007.
A. Mochizuki, H. Shirahama, and T. Hanyu, "Design and Evaluation of a 54 × 54-bit Multiplier Based on Differential-Pair Circuitry," IEICE Trans. Electron., vol. E90-C, no. 4, pp. 683-691, Apr. 2007.

Internationl Conference Papers

N. Onizawa, T. Ikeda, T. Hanyu, and V. C. Gaudet, "3.2-Gb/s 1024-b Rate-1/2 LDPC Decoder Chip Using a Flooding-Type Update-Schedule Algorithm," Proc. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS), pp. 217-220, Aug. 2007.
K. Kimura and T. Hanyu, "A Standby-Power-Free TCAM Based on TMR Logic," Proc. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS), pp. 855-858, Aug. 2007.
H. Shirahama, A. Mochizuki, T. Hanyu, M. Nakajima, and K. Arimoto, "Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor," Proc. 37th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 43~1-43~6, May 2007.
T. Takahashi, K. Mizusawa, and T. Hanyu, "Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme," Proc. 37th IEEE International Symposium on Multiple-Valued Logic (ISMVL), 44~1-44~6, May 2007.
A. Mochizuki, M. Miura, and T. Hanyu, "High-Performance Multiple-Valued Comparator Based on Active-load Dual-Rail Differential Logic for Crosstalk-Noise Reduction," Proc. 37th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 57~1-57~6, May 2007.
S. Matsunaga, T. Hanyu, H. Kimura, T. Nakamura and H. Takasu, "Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic," Proc. Asia and South Pacific Design Automation Confrence (ASP-DAC), pp. 116-117, Jan. 2007.

[2006]

Journal Papers

N. Onizawa and T. Hanyu, "Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic," IEICE Trans. Electron., vol. E89-C, no. 11, pp. 1575-1580, Nov. 2006.
A. Mochizuki, H. Shirahama, and T. hanyu, "Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic," IEICE Trans. Electron., vol. E89-C, no. 11, pp. 1591-1597, Nov. 2006.
T. Takahashi and T. Hanyu, "Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing," IEICE Trans. Electron., vol. E89-C, no. 11, pp. 1598-1604, Nov. 2006.

Internationl Conference Papers

A. Mochizuki and T. Hanyu, "Highly Reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic," Proc. 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 5~1-5~6, May 2006.
A. Mochizuki, T. Kitamura, H. Shirahama, and T. Hanyu, "Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits," Proc. 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 14~1-14~6, May 2006.
H. Kimura, Y. Fujimori, T. Nakamura, H. Takasu, and T. Hanyu, "Ferroelectric-based Logic circuit and Its Application to Content Addressable Memory," Proc. International Meeting for Future of Electron Devices, Kansai(IMFEDK), pp. 41-42, Apr. 2006.

[2005]

Journal Papers

A. Mochizuki, T. Hanyu, and M. Kameyama, "Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic," International Journal of Multiple-Valued Logic and Soft Computing, vol.11, no. 5-6, pp. 481-498, 2005.
T. Takahashi and T. Hanyu, "Control Signal Multiplexing Based Asynchronous Data Transfer Scheme Using Multiple-Valued Bidirectional Current-Mode Circuits," International Journal of Multiple-Valued Logic and Soft Computing, vol. 11, no. 5-6, pp. 499-517, 2005.
A. Mochizuki, H. Kimura, M. Ibuki, and T. Hanyu, "TMR-Based Logic-in-Memory Circuit for Low-Power VLSI," IEICE Trans. Fundamentals, vol.E88-A, no.6, pp.1408-1415, Jun. 2005.

Internationl Conference Papers

A. Mochizuki and T. Hanyu, "A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry," Symposium on VLSI Circuits, Digest of Technical Papers, pp. 264-267, Jun. 2005.
N. Onizawa, A. Mochizuki, T. Hanyu, and V. C. Gaudet, "Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders," Proc. 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 138-143, May 2005.

[2004]

Journal Papers

A. Mochizuki, D. Nishinohara, and T. Hanyu, "Low-power Motion-Vector Detection VLSI Processor Based on Pass-Gate Logic with Dynamic Supply-Voltage/Clock-Frequency Scaling," IEICE Trans. Electron., vol.E87-C, no. 11, pp.1876-1883, Nov. 2004.
A. Mochizuki, T. Takeuchi, and T. Hanyu, "Dynamically Function-Programmable Bus Architecture for High-Throughput Intra-Chip Data Transfer," IEICE Trans. Electron., vol.E87-C, no. 11, pp. 1915-1922, Nov. 2004.
T. Takahashi, N. Onizawa, and T. Hanyu, "Differential Operation Oriented Multiple-Valued Encoding and Circuit Realization for Asynchronous Data Transfer," IEICE Trans. Electron., vol. E87-C, no. 11, pp. 1928-1934, Nov. 2004.
H. Kimura, T. Hanyu, M. Kameyama, Y. Fujimori, T. Nakamura, and H. Takasu, "Complementary Ferroelectric-Capacitor Logic for Low-Power Logic-in-Memory VLSI," IEEE Journal of Solid-State Circuits, vol.39, no.6, pp. 919-926, Jun. 2004.
T. Takahashi, T. Hanyu, and M. Kameyama, "Asynchronous Data Transfer Scheme Based on Simultaneous Control in a Bidirectional Way and Its VLSI Design," IEICE Trans. Electron. (Japanese), vol. J87-C, no. 5, pp.459-468, May 2004.
A. Mochizuki and T. Hanyu, "Low-Power Multiple-Valued Current-Mode Logic Using Substrate Bias Control," IEICE Trance. Electron., vol. E87-C no. 4, pp. 582-588, Apr. 2004.

Internationl Conference Papers

A. Mochizuki, D. Nishinohara, and T. Hanyu, "Low-Powor Pipelined VLSI System Using a Power-Supply-Controlled CMOS Pass-Gate Network and Its Application," Proc. International Conference on Circuits/Systems, Computers and Communications, 6CIL-5~1-6CIL-5~4, Jul. 2004.
H. Kimura, M. Ibuki, and T. Hanyu, "TMR-Based Logic-in-Memory Circuit for Low-Power VLSI," Proc. International Conference on Circuits/Systems, Computers and Communications, 8C3L-3~1-8C3L-3~4, Jul. 2004.
T. Takahashi and T. Hanyu, "Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous Communication," Proc. 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 20-25, May 2004.
A. Mochizuki, T. Takeuchi, and T. Hanyu "Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding," Proc. 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp.192-197, May 2004.
H. Kimura, K. Pagiamtzis, A. Sheikholeslami, and T. Hanyu, " A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ," Proc. 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 340-345, May 2004.

[2003]

Journal Papers

H. Kimura, T. Hanyu, M. Kameyama, Y. Fujimori, T. Nakamura, and H. Takasu, "Design of Ferroelectric-Based Logic-in-Memory VLSI," IEICE Trans. Electron. (Japansese), col.J86-C no. 8, pp. 886-893, Aug. 2003.
T. Ike, T. Hanyu, M. Kameyama, "Optimal Design of a Dual-Rail Multiple-Valued Current-Mode Integrated Circuit Based on Voltage Swing Minimimzation," Journal of Multiple-Valued Logic & Soft Computing, vol.9, no.1, pp.5-21, 2003.
H. Kimura, T. Hanyu, and M. Kameyama, "Multiple-Valued Logic-in-Memory VLSI Using MFSFETs and Its Applications," Journal of Multiple-Valued Logic & Soft Computing, vol.9, no. 1, pp. 23-42, 2003.

Internationl Conference Papers

T. Hanyu, T. Takahashi, and M. Kameyama, "Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current-Mode Logic," Proc. 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 99-104, May 2003.
T. Hanyu, A. Mochizuki, and M. Kameyama, "Multiple-Valued Dynamic Source-Coupled Logic," Proc. 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 207-212, May 2003.
Y. Fujimori, T. Nakamura, H. Takasu, H. Kimura, T. Hanyu, and M. Kameyama, "Ferroelectric Non-volatile Logic Devices," Proc. International Symposium on Integrated Ferroelectrics (ISIF), pp. 218-219, Mar. 2003.
H. Kimura, T. Hanyu, M. Kameyama, Y. Fujimori, T. Nakamura, and H. Takasu, "Complementary Ferroelectric-Capacitor Logic for Low-Power Logic-in-Memory VLSI" IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pp. 160-161, Feb. 2003.