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PROFILE

NameDaisuke Suzuki
BirthdayAugust 16, 1981
TitleDoctor
E-MAILdaisuke.suzuki.e6(at mark)tohoku.ac.jp


Academic Career

March, 2004 Received the B. E. Degree in the Dept. of Electronic Eng., Tohoku University
March, 2006 Received the M. E. Degree in the Dept. of Electronic Eng., Tohoku University
Sept., 2009Received the D. E. Degree in the Dept. of Electronic Eng., Tohoku University


Professional Career

October, 2009-March, 2010Postdoctoral Research Fellow, Research Institute of Electrical Communication, Tohoku University
April, 2010-Present Research Associate, Center for Spintronics Integrated Sysyems, Tohoku University
April, 2014-Present Assistant Professor, Center for Innovative Integrated Electronic Systems, Tohoku University


Academic Society Members

IEEE (Institute of Electrical and Electronics Engineers)
IEICE (Institute of Electronics, Information and Communication Engineers)
IPSJ (Information Processing Society of Japan)


Academic Activities

International
MWSCAS2012 Technical Reviewer 2012.5-2012.8


Awards

The paper award from IEICE Electronics Society May, 2010


Publications (Journal papers)

　 Title Journal Vol. No. Pages Year Authors
1 Design of a Lookup Table Circuit Based on TMR Logic and Its Application to an Immediate Wake-Upable FPGA (in Japanese) IEICE Transactions J92-C 7 233-240 2009 D. Suzuki, M. Natsui, T. Hanyu
2 Six-input lookup table circuit with 62% fewer transistors using nonvolatile logic-in-memory architecture with series/parallel-connected magnetic tunnel junctions Journal of Applied Physics 111 7 07E318-1~3 2012 D. Suzuki, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu
3 Compact Nonvolatile Logic Element Using a Magnetic-Tunnel-Junction and Metal-Oxide-Semiconductor Hybrid Structure Japanese Journal of Applied Physics 51   04DM02 2012 D. Suzuki, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu
4 A 71%-Area-Reduced Six-Input Nonvolatile Lookup-Table Circuit Using a Three-Terminal Magnetic-Tunnel-Junction-Based Single-Ended Structure Japanese Journal of Applied Physics 52   04CM04 2013 D. Suzuki, Yuhui Lin, M. Natsui, and T. Hanyu
5 Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications IEICE Electronics Express 10 23 20130772 2013 D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, K. Kinoshita, H. Sato, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu
6 Design and Evaluation of a 67% Area-Less 64-bit Parallel Reconfigurable 6-Input Nonvolatile Logic Element Using Domain-Wall Motion Devices Japanese Journal of Applied Physics 53 4S 04EM03 2014 D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu
7 Design and Fabrication of a Perpendicular-MTJ-Based Nonvolatile Programmable Switch Achieving 40% Less Area Using Shared-Control Transistor Structure Journal of Applied Physics 115 17 17B742 2014 D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, K. Kinoshita, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu
8 A Compact Low-Power Nonvolatile Flip-Flop Using Domain-Wall-Motion-Device-Based Single-Ended Structure IEICE Electronics Express 11 13 20140296 2014 D. Suzuki, N. Sakimura, M. Natsui, A. Mochizuki, T. Sugubayashi, T. Endoh, H. Ohno, and T. Hanyu
9 Cost-Efficient Self-Terminated Write Driver for Spin-Transfer-Torque RAM and Logic IEEE Transactions on Magnetics 50 11 3402104~1-3402104~4 2014 D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu
10 Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction IEEE Journal of Solid-State Circuits 50 2 476-489 2015 M. Natsui, D. Suzuki, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, T. Sugibayashi, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu
11 Magnetic-Tunnel-Junction Based Low-Energy Nonvolatile Flip-Flop Using An Area-Efficient Self-Terminated Write Driver Journal of Applied Physics 117 17B504-1~17B504-3 2015 D. Suzuki and T. Hanyu
12 Nonvolatile Field-Programmable Gate Array Using 2-Transistor-1-Magnetic-Tunnel-Junction-Vell-Based Multi-Context Array for Power and Area Efficient Dynamically Reconfigurable Logic Japanese Journal of Applied Physics to be bublished 2015 D. Suzuki and T. Hanyu


Publications (International Conference and Symposium, Refereed)

　 Title Journal Vol. Pages Year Authors
1 TMR-Logic-Based LUT for Quickly Wake-Up FPGA 51st IEEE Midwest Symposium on Circuits and Systems (MWSCAS)   326-329 2008 D. Suzuki, T. Endoh and T. Hanyu
2 Fabrication of a Nonvolatile Lookup-Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array IEEE 2009 Symposium on VLSI Circuits Digest of Technical Papers C-8 80-81 2009 D. Suzuki, M. Natsui, S. Ikeda, H. Hasegawa, K. Miura, J. Hayakawa, T. Endoh, H. Ohno, and T. Hanyu
3 Design of a Process-Variation-Aware Nonvolatile MTJ-Based Lookup-Table Circuit International Conference on Solid State Devices and Materials (SSDM) K-9-4 1146-1147 2010 D. Suzuki, M. Natsui, H. Ohn,o and T. Hanyu
4 A Compact Nonvolatile Logic Element Using an MTJ/MOS-Hybrid Structure International Conference on Solid State Devices and Materials (SSDM) N-8-2 1464-1465 2011 D. Suzuki, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu
5 50%-Transistor-Less Standby-Power-Free 6-input LUT Circuit Using Redundant MTJ-Based Nonvolatile Logic-in-Memory Architecture 56th Annual Conference on Magnetism and Magnetic Materials(MMM) GD-07 480 2011 D. Suzuki, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu
6 Building Blocks to Use in Innovative non-Volatile FPGA Architecture Based on MTJs IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2012 L. Montesi, Z. Zilic, T. Hanyu, and D. Suzuki
7 Area-Efficient LUT Circuit Design Based on Asymmetry of MTJ's Current Switching for a Nonvolatile FPGA 55th IEEE Midwest Symposium on Circuits and Systems (MWSCAS) 334-337 2012 D. Suzuki, M. Natsui, and T. Hanyu
8 Design of Compact Nonvolatile Lookup-Table Circuit Using Three-Terminal Magnetic-Tunnel-Junction-Based Single-Ended Structure International Conference on Solid State Devices and Materials (SSDM) P-12-1 To be presented. 2012 D. Suzuki, Y. Lin, M. Natsui, and T. Hanyu
9 Nonvolatile Logic-in-Memory Array Processor in 90nm MTJ/MOS Achieving 75% Leakage Reduction Using Cycle-Based Power Gating 2013 IEEE International Solid-State Circuits Conference (ISSCC2013) 193-195 2013 M. Natsui, D. Suzuki, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, T. Sugibayashi, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu
10 Design of a Three-Terminal MTJ-Based Nonvolatile Logic Element with a 2-ns 64-Bit-Parallel Reconfiguration Capability International Conference on Solid State Devices and Materials (SSDM) PS-12-5 386-387 2013 D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu
11 Fabrication of a Perpendicular-MTJ-Based Compact Nonvolatile Programmable Switch Using Shared-Write-Control-Transistor Structure 58th Annual Conference on Magnetism and Magnetic Materials (MMM) CD-05 233 2013 D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, K. Kinoshita, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu
12 Optimally Self-Terminated Compact Switching Circuit Using Continuous Voltage Monitoring Achieving High Read Margin for STT MRAM and Logic IEEE International Magnetic Conference FU-19 2506-2507 2014 D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu
13 Nonvolatile FPGA Using 2T-1MTJ-Cell-Based Multi-Context Array for Power and Area Efficient Dynamically Reconfigurable Logic International Conference on Solid State Devices and Materials (SSDM) To be presented 2014 D. Suzuki and T. Hanyu


Publications (International Conference and Symposium, Non-Refereed)

　 Title Journal Vol. Pages Year Authors
1 Ferroelectric-Based Cellular Array VLSI for High-Performance Fluid Analysis Proc. 2nd Int. workshop of Tohoku University and Yengnam University   77-78 2005 D. Suzuki and T. Hanyu
2 Design of a Fluid Analysis Simulator Based on Lattice Gas Cellular Automaton Proc. 3rd Int. workshop of Yengnam University and Tohoku University   132-134 2006 D. Suzuki and T. Hanyu
3 Design of a Fluid Analysis Simulator Based on Lattice Gas Cellular Automaton Proc. Joint Int. Conf. 4th Int. Symp. Syst. Construction of Global-Network-Oriented Information Electronics (IGNOIE-COE) and Student Organizing International Mini-Conf. Information Electronics Systems (SOIM)   330-331 2007 D. Suzuki and T. Hanyu
4 Nonvolatile Field-Programmable Gate Array Using MOS/MTJ Hybrid Structure Proc. The 1nd Student Organizing International Mini-Conf. Information Electronics Systems (SOIM)   181-182 2008 D. Suzuki and T. Hanyu
5 Nonvolatile Field-Programmable Gate Array Using MOS/MTJ Hybrid Structure RIEC-CNSI Workshop 2009 on Nanoelectronics, Spintronics and Photonics   40 2009 D. Suzuki, M. Natsui and T. Hanyu
6 Design of a Nonvolatile Lookup Table Circuit Based on TMR Logic for an Immediate Wakeup FPGA Proc. The 2nd Student Organizing International Mini-Conf. Information Electronics Systems (SOIM)   135-136 2009 D. Suzuki, M. Natsui and T. Hanyu
7 Considerations of Incorporating MTJ-based Blocks into Existing FPGA Architecture Families 20th International Workshop on Post-Binary Ultra Large Scale Integrated Systems     2011 L. Montesi, Z. Zillic, D. Suzuki, and T. Hanyu
8 Design of a Compact MTJ/MOS-Hybrid Logic Element for a Nonvolatile Field-Programmable Gate Array the 2nd CSIS International Symposium on Spintronics-Based VLSIs and the 8th RIEC International Workshop on Spintronics P-18 44 2012 D. Suzuki and T. Hanyu
9 Nonvolatile Look-up Table Circuit Using Three Terminal MTJ-Based Logic-in-Memory Architecture the 3rd CSIS International Symposium on Spintronics-Based VLSIs and the 8th RIEC International Workshop on Spintronics P-06 32 2013 D. Suzuki and T. Hanyu
　
Dec. 2013