27th International Workshop
May 15th, 2018, Linz, Austria
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The 27th International Workshop on Post-Binary ULSI Systems (ULSIWS) will be held in conjunction with the IEEE 48th Annual International Symposium on Multiple-Valued Logic (ISMVL2018) on May 15, 2018 in Linz, Austria. You are invited to submit an original paper, survey or tutorial paper on any subject in the area of new devices for ULSI systems, high-performance circuits and design, and new LSI architecture. Proposals for special sessions concerning the above topics are also welcome.
Updates
- Tentative Program has been updated (April 12, 2018)
- Post-Binary ULSI Workshop 2018 Website opened (Nov. 24, 2017)
Important Dates
- March 1, 2018: Proposal of Special Session due
- March 14, 2018: Notification of Special Session
- April 1, 2018: Submission of Abstract due
- April 7, 2018: Notification of Paper Acceptance
- April 21, 2018: Submission of Final Papers due
- May 1, 2018: Pre-Registration Deadline
- May 15, 2018: Workshop
Venue and Accommodation
- Symposium Venue
The symposium venue is take place at the Johannes Kepler University of Linz (JKU) in the building "Uni Center", that is the same of the ISMVL2018. For more detail, please see ISMVL2018 venue information. - Prof. Shinya Takamaeda-Yamazaki (Hokkaido University, Japan)
- Title: Making Efficient Quantized Neural Network Engine by Hardware/Algorithm Co-Design
- Biography: Shinya Takamaeda received the B.E, M.E, and D.E degrees from Tokyo Institute of Technology, Japan in 2009, 2011, and 2014 respectively. From 2011 to 2014, he was a JSPS research fellow (DC1). From 2014 to 2016, he was an assistant professor of Nara Institute of Science and Technology, Japan. Since 2016, he has been an associate professor of Hokkaido University, Japan. His research interests include FPGA computing, high level synthesis, and machine learning. He is a member of IEEE, IEICE, and IPSJ.
- Algebra and Formal Aspects
- ATPG and SAT
- Automatic Reasoning
- Bio-Inspired and Novel
- Hardware Algorithms
- Communication Systems
- Computer Arithmetic
- Computer Security
- Data Bases
- Data Mining
- Decision Diagram
- Fuzzy Logic and Soft Computing
- Image Processing
- Logic Design and Switching Theory
- Logic Programming
- Machine Learning and Robotics
- Mathematical Fuzzy Logic
- Medical and Wellness Care Technology
- Nano Technology and Computer Security
- Opto-Electronics
- Index Generation Functions
- Quantum Computing
- Quantum Cryptography
- Quantum Devices
- Signal Processing
- Single Electrons
- Spectral Techniques
- Superconductivity
- Web Intelligence
- Verification
- Philosophical Aspects
- Please convert the manuscript file into a PDF file using the Adobe Acrobat Distiller. All fonts used in the manuscript must be embedded in the PDF file in converting.
- Please send the PDF file via e-mail to natsui{at}riec.tohoku.ac.jp.
- Paper Size
The manuscript should be clearly printed on single-sided A4 (210mm x 297mm) or US letter (8.5 x 11 inch) paper. - Margins
The left and right margins are the same and are to be 25mm. The top and bottom margins are to be 30mm and 25mm, respectively. - Language
All papers must be written in English. - Restriction on the Number of Pages
The number of pages for a manuscript is not strictly restricted. But, 6 to 8 pages for Regular Sessions are preferred. - Page Numbering
Please do not type page numbers on the camera-ready manuscript. - Details
We recommend you use the IEEE format to prepare your camera-ready manuscript. You can get the Microsoft Word style file and LaTeX style files.
MS Word style file: MS Word Template file
LaTeX style files: For Linux/Unix, IEEEtran.tar.gz
For PC and Mac, IEEEtran.zip - March 1, 2018: Proposal of Special Session due
- March 14, 2018: Notification of Special Session
- April 1, 2018: Submission of Abstract due
- April 7, 2018: Notification of Paper Acceptance
- April 21, 2018: Submission of Final Papers due
Registration (Note, be subject to change)
- Registration fee is free.
- To all participants who make a registration in advance, the conference proceedings will be distributed and light meals will be served for lunch.
- To make a pre-registration please send email notification to Masanori Natsui (natsui{at}riec.tohoku.ac.jp) by (TBD).
- On-site registration will be accepted, but we cannot guarantee your proceeding and lunch service.
Committee
The ULSIWS2018 is organized by following members. If you have questions, do not hesitate to contact us. Best way to reach us is via mail.Workshop Chair:
- Masanori Natsui (Tohoku University, Japan), natsui{at}riec.tohoku.ac.jp
Local Arrangement Chair
Sponsored by
- Japan Research Group on Multiple-Valued Logic
Link
- The 48th International Symposium on Multiple-Valued Logic (ISMVL2018)
- Past Workshops
- ULSIWS2017 [Novi Sad, Serbia]
- ULSIWS2016 [Hokkaido,Japan]
- ULSIWS2015 [Waterloo,Canada]
- ULSIWS2014 [Bremen,Germany]
- ULSIWS2013 [Toyama,Japan]
- ULSIWS2012 [Victoria,Canada]
- ULSIWS2011 [Tuusula,Finland]
- ULSIWS2010 [Barcelona,Spain]
- ULSIWS2009 [Okinawa,Japan]
- ULSIWS2008 [Texas,U.S.A.]
- ULSIWS2007 [Oslo,Norway]
- ULSIWS2006 [Singapore,Singapore]
- ULSIWS2005 [Calgary,Canada]
- ULSIWS2004 [Toronto,Canada]
Program
Tentative Program
Invited Talk
We are proud to announce an invited speaker.Call for Papers and Sessions
You are invited to submit an original paper, survey or tutorial paper on any subject in the area of new devices for ULSI systems, high-performance circuits and design, and new LSI architecture. The topics of interest include but not limited to:|
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Proposals for special sessions concerning the above topics are also welcome. Special session proposals should be submitted to the Workshop Chair Masanori Natsui (natsui{at}riec.tohoku.ac.jp).